DM385的两片DDR是怎么等长,看起来很奇怪,
NOTE:
1) Through Hole Test points are used to
check compliance with the routing guidelines.
This helps to generate the Net length Report.
2) Designers need to replace Test point with
a Via of the same size.
不知道具体怎么做到的
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DM385的两片DDR是怎么等长,看起来很奇怪,
NOTE:
1) Through Hole Test points are used to
check compliance with the routing guidelines.
This helps to generate the Net length Report.
2) Designers need to replace Test point with
a Via of the same size.
不知道具体怎么做到的
这个就是个标准的T net, T型走线。也就是说一个net上连着三个pin,所以这个信号线的拓扑是T形的。而为了信号质量的问题,我们一般把交点放在通孔上。
T形走线是DDR layout拓扑的一种。你提到PCB上的是用的daisy chain的方式。
回到你问的那个问题,在信号线上添加额外的 test point 会影响信号质量,所以建议直接拿走线上本来的通孔作为test point