TMS320F28034的TZSEL使能问题

在初始化TZSEL的时候发现:

     EPwm1Regs.TZSEL.bit.DCAEVT2 = 1;
     EPwm1Regs.TZSEL.bit.DCBEVT2 = 1;

          置位正常(已跑程序验证),用示波器测量斩波现象,同等条件下使能该位后EPwm1不发波,不使能该位或是把该位置零EPwm1发波,这个结果跟官网公布的资料相反

,请朋友们给予指导,感谢!附ePWM1配置如下:

void InitEPwm1Driver(void)
{
EALLOW;
EPwm1Regs.TBPRD = 3000;////PFSB_PERIOD,1250-48K
EPwm1Regs.TBPHS.all = 0;
EPwm1Regs.TBCTR = 0;

// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; //
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;//Count equal to zero; have a syn output
EPwm1Regs.TBCTL.bit.SWFSYNC = 0;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; //
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.PHSDIR = 1;
EPwm1Regs.TBCTL.bit.FREE_SOFT = 3; //
// Setup compare
EPwm1Regs.CMPA.half.CMPA = 1500;
EPwm1Regs.CMPB = 1500;
EPwm1Regs.TBPHS.half.TBPHS = 0;
// Setup CMPCTL
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;/////
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.ZRO = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.CBU = AQ_SET;

//EPwm1Regs.AQSFRC.bit.RLDCSF = 0;

//Set DeadBand
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;//
EPwm1Regs.DBCTL.bit.IN_MODE = 0x0;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm1Regs.DBFED = 300;//
EPwm1Regs.DBRED = 300;//
//EPwm1Regs.DBCTL.bit.HALFCYCLE = 1;

// // Set ETSEL
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // 2:0 EPWMxINTn Select
EPwm1Regs.ETSEL.bit.INTEN = ET_ENABLE; // 3 EPWMxINTn Enable
EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTRU_CMPA; // 10:8 Start of conversion A Select
EPwm1Regs.ETSEL.bit.SOCAEN = ET_ENABLE; // 11 Start of conversion A Enable
EPwm1Regs.ETSEL.bit.SOCBSEL = ET_CTRU_CMPB; // 14:12 Start of conversion B Select
EPwm1Regs.ETSEL.bit.SOCBEN = ET_ENABLE; // 15 Start of conversion B Enable

EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // 1:0 EPWMxINTn Period Select
EPwm1Regs.ETPS.bit.INTCNT = 0; // 3:2 EPWMxINTn Counter Register
EPwm1Regs.ETPS.bit.SOCAPRD = ET_1ST; // 9:8 EPWMxSOCA Period Select
EPwm1Regs.ETPS.bit.SOCACNT = 0; // 11:10 EPWMxSOCA Counter Register
EPwm1Regs.ETPS.bit.SOCBPRD = 1; // 13:12 EPWMxSOCB Period Select
EPwm1Regs.ETPS.bit.SOCBCNT = 0; // 15:14 EPWMxSOCB Counter Register
/////////////////////////////////////////////////////
//EPwm1Regs.TZSEL.bit.DCAEVT2 = 1;////
//EPwm1Regs.TZSEL.bit.DCAEVT2 = 0;////
//EPwm1Regs.TZSEL.bit.DCBEVT2 = 0;////
//EPwm1Regs.TZSEL.bit.DCBEVT2 = 1;
EPwm1Regs.TZSEL.bit.CBC1=1;
EPwm1Regs.TZEINT.bit.CBC=1;

// What do we want the TZ1 and TZ2 to do
EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO;

EPwm1Regs.TZDCSEL.bit.DCAEVT2 = TZ_DCAH_HI;
EPwm1Regs.TZDCSEL.bit.DCBEVT2 = TZ_DCAH_HI;

EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_COMP1OUT; // DCAH = Comparator 2 output
EDIS;
}

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