#include "common.h"
#include "gpio.h"
#include "ssp.h"
#include "dbmessage.h"
int g_current_bank;
void SysInit(void)
{
SSPINIT spi_cfg;
spi_cfg.PortEnable = TRUE;
spi_cfg.PortMode = SSP_MASTER;
spi_cfg.XFERMode = SSP_XFER_AUTO;
spi_cfg.ClockRateHz = 25000000;
spi_cfg.DataBits = SSP_16BITS;
spi_cfg.*** = SSP_HIGH_IDLE;
spi_cfg.*** = SSP_XFR_2ND_CLK_EDGE;
spi_cfg.SPIDuplex = SSP_FULLDUPLEX;
spi_cfg.ChipSelect = SSP_CS0;
spi_cfg.AssertDelay = 0;
spi_cfg.DeAssertDelay = 0;
spi_cfg.InterWordDelay = 0;
SSP_InitConfigData(SSP_PORT1, SSP_CS0, &spi_cfg);
}
//-------------------------------------------------------------
// C787 Register read access
//-------------------------------------------------------------
unsigned int read_C787( int ad )
{
int bank, addr, nbyte, wbyte, rbytes;
unsigned int dt;
uint16 rdt, bdt, wdt, rdbuf;
int08 rc1, rc2, rd1byte;
uint16 wbuf;
uint08 rbuff[4];
uint32 wtimeout, rtimeout, sizewritten, sizereaded;
uint32 outclk;
dt = 0;
bank = ( ad >> 16 ) & 0xff;
addr = ( ad >> 8 ) & 0xff;
nbyte = ad & 0xff;
SSP_ReservePortSemaphore(SSP_PORT1, 10);
if ( bank != g_current_bank ) {
g_current_bank = bank;
bdt = ((((0x00 | 0x80) << 8) & 0xff00) | (bank & 0xff));
rc1 = SSP_PolledWrite(SSP_PORT1, SSP_CS0, 2, &bdt, 100, &sizewritten);
// dbmsg_ftrace(DBM_C787, "SSP_PolledWrite addr = %06x, rc = %d, wbyte = %d\r\n", addr, rc1, sizewritten);
}
while ( nbyte > 0 ) {
nbyte--;
dt = ( dt << 8 );
wbuf = (0x00 << 8) | ((addr + nbyte) & 0x7f);
rc2 = SSP_PolledWriteRead(SSP_PORT1, SSP_CS0, 2, &wbuf, 100, &sizewritten, 1, (uint16*)&rd1byte, 100, &sizereaded);
dt = dt + rd1byte;
}
SSP_ReleasePortSemaphore(SSP_PORT1);
return dt;
}
//-------------------------------------------------------------
// C787 Register write access
//-------------------------------------------------------------
void write_C787( int ad, unsigned int dt, int bk_offset, int force )
{
int bank, addr, nbyte;
uint16 bdt, wdata;
uint32 wbyte;
int08 rc1, rc2;
//-------------------------------------------------------------
bank = (ad >> 16) & 0xff;
addr = (ad >> 8) & 0xff;
nbyte = ad & 0xff;
bank += bk_offset;
//-------------------------------------------------------------
SSP_ReservePortSemaphore(SSP_PORT1, 10);
if ( bank != g_current_bank ) {
g_current_bank = bank;
bdt = ((((0x00 | 0x80) << 8) & 0xff00) | (bank & 0xff));
rc1 = SSP_PolledWrite(SSP_PORT1, SSP_CS0, 2, &bdt, 100, &wbyte);
}
//-------------------------------------------------------------
while ( nbyte > 0 ) {
wdata = ((((addr | 0x80) << 8) & 0xff00) | (dt & 0xff));
rc2 = SSP_PolledWrite(SSP_PORT1, SSP_CS0, 2, &wdata, 100, &wbyte);
addr++;
dt = ( dt >> 8 );
nbyte--;
}
SSP_ReleasePortSemaphore(SSP_PORT1);
}