DSP与FPGA通过EMIF进行通信,轮询方式读数,DMA方式向FPGA写数,在用仿真器调试时,时序是正确的,有读有写,但是将程序固化后,再看时序,没有DMA方式通过EMIF向FPGA写的时序了,不知道是什么影响了程序,请大神指教。
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
DSP与FPGA通过EMIF进行通信,轮询方式读数,DMA方式向FPGA写数,在用仿真器调试时,时序是正确的,有读有写,但是将程序固化后,再看时序,没有DMA方式通过EMIF向FPGA写的时序了,不知道是什么影响了程序,请大神指教。
芯片boot后,bootloader把时钟关掉了。在自已的初始化函数里重新使能一下就好了。
3.3.1.2 Peripheral Clock State
The clock and reset state of each of peripheral is controlled through a set of system registers. The
peripheral clock gating control registers (PCGCR1 and PCGCR2) are used to enable and disable
peripheral clocks. The peripheral software reset counter register (PSRCR) and the peripheral reset control
register (PRCR) are used to assert and de-assert peripheral reset signals.
At hardware reset, all of the peripheral clocks are off to conserve power. After hardware reset, the DSP
boots via the bootloader code in ROM. During the boot process, the bootloader queries each peripheral to
determine if it can boot from that peripheral. In other words, it reads each peripheral looking for a valid
boot image file. At that time, the individual peripheral clocks will be enabled for the query and then
disabled again when the bootloader is finished with the peripheral. By the time the bootloader releases
control to the user code, all peripheral clocks will be off and all domains in the ICR, except the CPU
domain, will be idled.