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请教各位前辈,关于全差动放大器的噪声分析问题,非常感谢!



如图,信号进入ADC前,被比例缩小了4倍,比如±10V的输入信号,进ADC后变成±2.5V(加共模),想问下噪声会不会被同样缩小?如果不会,是否这种电路拓扑会降低系统的信噪比?感谢各位前辈回答。