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EMIF NOR模式下,SYSBIOS工程二次加载(Secondary BOOT)无中断产生

Other Parts Discussed in Thread: SYSBIOS

目前,对于裸机工程,可以实现二次加载,即程序固化到flash的1k后地址单元中,前面1K地址实现程序搬移。但是对于SYSBIOS工程,一直没成功。目前在测试一个SRIO的SYSBIOS工程的二次启动。经过测试,SRIO初始化成功,可以link,收发数据,但是,无法接收到对方的Doorbell门铃中断,请问该如何排查和解决。boot.asm文件可以实现程序的正确搬移,已验证。

附上linker.cmd文件。(这里直接修改cmd文件,只是做测试用,最终还是需要修改配置文件)

--args 0x0
-heap 0x0
-stack 0x1000

MEMORY
{
L2SRAM (RWX) : org = 0x10800000, len = 0x80000
MSMCSRAM (RWX) : org = 0xc000000, len = 0x400000
DDR3 : org = 0x80000000, len = 0x20000000
BOOT (R): o = 0x70000000 l = 0x00000100
INTVEC (R): o = 0x70000100 l = 0x00001000
EMIF16_CS2 (R): o = 0x70001100 l = 0x003FE000
}

xdc_runtime_Startup__EXECFXN__C = 1;
xdc_runtime_Startup__RESETFXN__C = 1;
TSK_idle = ti_sysbios_knl_Task_Object__table__V + 80;

SECTIONS
{
.boot_sect > BOOT
.text: load > EMIF16_CS2 , run=L2SRAM, LOAD_START(FLASH_TEXT_START),RUN_START(RAM_TEXT_START), SIZE(TEXT_SIZE)
.ti.decompress: load > L2SRAM
.stack: load > L2SRAM
GROUP: load > MSMCSRAM
{
.bss:
.neardata:
.rodata:
}
.cinit: load > EMIF16_CS2
.pinit: load > L2SRAM //Certain sections should not be split
.init_array: load > MSMCSRAM
.const: load > EMIF16_CS2
.data: load >> MSMCSRAM
.fardata: load >> MSMCSRAM
.switch: load > EMIF16_CS2
.sysmem: load > MSMCSRAM
.far: load >> MSMCSRAM
.args: load > MSMCSRAM align = 0x4, fill = 0 {_argsize = 0x0; }
.cio: load >> MSMCSRAM
.ti.handler_table: load > L2SRAM
.c6xabi.exidx: load > L2SRAM
.c6xabi.extab: load >> L2SRAM
sharedL2: load > MSMCSRAM
systemHeap: load > MSMCSRAM
.cppi: load > MSMCSRAM
.qmss: load > MSMCSRAM
.code: load > MSMCSRAM
.vecs: load > INTVEC, run=MSMCSRAM, LOAD_START(FLASH_VECT_START),RUN_START(RAM_VECT_START), SIZE(VECT_SIZE)
platform_lib: load > MSMCSRAM
.DbgSection: load > MSMCSRAM
.far:taskStackSection: load > L2SRAM
.nimu_eth_ll2: load > L2SRAM
.resmgr_memregion: load > L2SRAM align = 0x80
.resmgr_handles: load > L2SRAM align = 0x10
.resmgr_pa: load > L2SRAM align = 0x8
.far:IMAGEDATA: load > L2SRAM align = 0x8
.far:NDK_OBJMEM: load > L2SRAM align = 0x8
.far:NDK_PACKETMEM: load > L2SRAM align = 0x80
.vecs_all: load > L2SRAM
xdc.meta: load > MSMCSRAM, type = COPY

}