AM335x 启动不了卡在KARNEL。。

我做了DRR的EMIF测试结果如下,不知道DDR是不是正常的。请各位大侠指导。

Switched to DAP_DebugSS
Read value of 2b94402e from Device_ID register.
CONTROL: device_id = 0x2b94402e
  * AM335x family
  * Silicon Revision 2.1

CONTROL: control_status = 0x00400324
  * SYSBOOT[15:14] = 01b (24 MHz)
CM_CLKSEL_DPLL_DDR = 0x00019017
  * DPLL_MULT = 400 (x400)
  * DPLL_DIV = 23 (/24)
CM_DIV_M2_DPLL_DDR = 0x00000201
  * CLKST = 1: M2 output clock enabled
  * DIVHS = 1 (/1)

DPLL_DDR Summary
 -> F_input = 24 MHz
 -> CLKOUT_M2 = DDR_PLL_CLKOUT = 400 MHz

EMIF: SDRAM_CONFIG = 0x61a45232
  * Bits 31:29 (reg_sdram_type) set for DDR3
  * Bits 28:27 (reg_ibank_pos) set to 0
  * Bits 26:24 (reg_ddr_term) set for RZQ/4 (001b)
  * Bits 22:21 (reg_dyn_odt) DDR3 dynamic ODT set to RZQ / 4
  * Bit  20    (reg_ddr_disable_dll) set to 0, DDR3 DLL enabled
  * Bits 19:18 (reg_sdram_drive) set for RZQ/7 (01b)
  * Bits 17:16 (reg_cwl) set for 0, CWL = 5
  * Bits 15:14 (reg_narrow_mode) set to 1 -> 16-bit EMIF interface
  * Bits 13:10 (reg_cl) set to 4 -> CL = 6
  * Bits 09:07 (reg_rowsize) set to 4 -> 13 row bits
  * Bits 06:04 (reg_ibank) set to 3 -> 8 banks
  * Bits 02:00 (reg_pagesize) set to 2 -> 10 column bits

EMIF: PWR_MGMT_CTRL = 0x00000000
 * Bits 10:8 reg_lp_mode set to 0, auto power management disabled
 * Warning: Bits 7:4 (reg_sr_tim) are in violation of Maximum Self-Refresh Command Limit
   -> Please see the silicon errata (DDR3: JEDEC Compliance for Maximum Self-Refresh Command Limit) for more details.
   -> This is only an issue if used in conjunction with reg_lp_mode=2.

DDR PHY: DDR_PHY_CTRL_1 = 0x00100007
  * Bits 9:8 (reg_phy_rd_local_odt) to 0 -> no termination
    -> Read termination is highly recommended in general for best DDR3 signal integrity
  * Bits 4:0 (reg_read_latency) set to 7
    -> If PHY_INVERT_CLKOUT=0, this is an appropriate value.
    -> If PHY_INVERT_CLKOUT=1, this is too small.
    -> PHY_INVERT_CLKOUT is a write-only register, so this needs to be
    -> inspected closely in the code and RatioSeed spreadsheet.

*********************
*** Register Dump ***
*********************

*(0x4c000000) = 0x40443403
*(0x4c000004) = 0x40000004
*(0x4c000008) = 0x61a45232
*(0x4c00000c) = 0x00000000
*(0x4c000010) = 0x00000c30
*(0x4c000014) = 0x00000c30
*(0x4c000018) = 0x0888c39b
*(0x4c00001c) = 0x0888c39b
*(0x4c000020) = 0x28247fda
*(0x4c000024) = 0x28247fda
*(0x4c000028) = 0x501f821f
*(0x4c00002c) = 0x501f821f
*(0x4c000038) = 0x00000000
*(0x4c00003c) = 0x00000000
*(0x4c000054) = 0x00ffff10
*(0x4c000058) = 0x8000140a
*(0x4c00005c) = 0x00021616
*(0x4c000080) = 0x03ee56a4
*(0x4c000084) = 0x0053ce48
*(0x4c000088) = 0x00010000
*(0x4c00008c) = 0x00000000
*(0x4c000090) = 0xcf5156e8
*(0x4c000098) = 0x00050000
*(0x4c00009c) = 0x00050000
*(0x4c0000a4) = 0x00000000
*(0x4c0000ac) = 0x00000000
*(0x4c0000b4) = 0x00000000
*(0x4c0000bc) = 0x00000000
*(0x4c0000c8) = 0x50074be4
*(0x4c0000d4) = 0x00000000
*(0x4c0000d8) = 0x00000000
*(0x4c0000dc) = 0x00000000
*(0x4c0000e4) = 0x00100007
*(0x4c0000e8) = 0x00100007
*(0x4c000100) = 0x00000000
*(0x4c000104) = 0x00000000
*(0x4c000108) = 0x00000000
*(0x4c000120) = 0x00000305

************************
*** IOCTRL Registers ***
************************

CONTROL: DDR_CMD0_IOCTRL = 0x000003bd
  * ddr_ba2 Pullup/Pulldown disabled
  * ddr_wen Pullup/Pulldown disabled
  * ddr_ba0 Pullup/Pulldown disabled
  * ddr_a5 Pullup/Pulldown disabled
  * ddr_ck Pullup/Pulldown disabled
  * ddr_ckn Pullup/Pulldown disabled
  * ddr_a3 Pullup/Pulldown disabled
  * ddr_a4 Pullup/Pulldown disabled
  * ddr_a8 Pullup/Pulldown disabled
  * ddr_a9 Pullup/Pulldown disabled
  * ddr_a6 Pullup/Pulldown disabled
  * Bits 9:5 control ddr_ck and ddr_ckn
    - Slew slowest
    - Drive Strength 10 mA
  * Bits 4:0 control ddr_ba0, ddr_ba2, ddr_wen, ddr_a[9:8], ddr_a[6:3]
    - Slew slowest
    - Drive Strength 10 mA
CONTROL: DDR_CMD1_IOCTRL = 0x000003bd
  * ddr_a15 Pullup/Pulldown disabled
  * ddr_a2 Pullup/Pulldown disabled
  * ddr_a12 Pullup/Pulldown disabled
  * ddr_a7 Pullup/Pulldown disabled
  * ddr_ba1 Pullup/Pulldown disabled
  * ddr_a10 Pullup/Pulldown disabled
  * ddr_a0 Pullup/Pulldown disabled
  * ddr_a11 Pullup/Pulldown disabled
  * ddr_casn Pullup/Pulldown disabled
  * ddr_rasn Pullup/Pulldown disabled
  * Bits 4:0 control ddr_15, ddr_a[12:10], ddr_a7, ddr_a2, ddr_a0, ddr_ba1, ddr_casn, ddr_rasn
    - Slew slowest
    - Drive Strength 10 mA
CONTROL: DDR_CMD2_IOCTRL = 0x000003bd
  * ddr_cke Pullup/Pulldown disabled
  * ddr_resetn Pullup/Pulldown disabled
  * ddr_odt Pullup/Pulldown disabled
  * ddr_a14 Pullup/Pulldown disabled
  * ddr_a13 Pullup/Pulldown disabled
  * ddr_csn0 Pullup/Pulldown disabled
  * ddr_a1 Pullup/Pulldown disabled
  * Bits 4:0 control ddr_cke, ddr_resetn, ddr_odt, ddr_csn0, ddr_[a14:13], ddr_a1
    - Slew slowest
    - Drive Strength 10 mA
CONTROL: DDR_DATA0_IOCTRL = 0x000003bd
  * ddr_d8 Pullup/Pulldown disabled
  * ddr_d9 Pullup/Pulldown disabled
  * ddr_d10 Pullup/Pulldown disabled
  * ddr_d11 Pullup/Pulldown disabled
  * ddr_d12 Pullup/Pulldown disabled
  * ddr_d13 Pullup/Pulldown disabled
  * ddr_d14 Pullup/Pulldown disabled
  * ddr_d15 Pullup/Pulldown disabled
  * ddr_dqm1 Pullup/Pulldown disabled
  * ddr_dqs1 and ddr_dqsn1 Pullup/Pulldown disabled
  * Bits 9:5 control ddr_dqs1, ddr_dqsn1
    - Slew slowest
    - Drive Strength 10 mA
  * Bits 4:0 control ddr_d[15:8], ddr_dqm1
    - Slew slowest
    - Drive Strength 10 mA
CONTROL: DDR_DATA1_IOCTRL = 0x000003bd
  * ddr_d0 Pullup/Pulldown disabled
  * ddr_d1 Pullup/Pulldown disabled
  * ddr_d2 Pullup/Pulldown disabled
  * ddr_d3 Pullup/Pulldown disabled
  * ddr_d4 Pullup/Pulldown disabled
  * ddr_d5 Pullup/Pulldown disabled
  * ddr_d6 Pullup/Pulldown disabled
  * ddr_d7 Pullup/Pulldown disabled
  * ddr_dqm0 Pullup/Pulldown disabled
  * ddr_dqs0 and ddr_dqsn0 Pullup/Pulldown disabled
  * Bits 9:5 control ddr_dqs0, ddr_dqsn0
    - Slew slowest
    - Drive Strength 10 mA
  * Bits 4:0 control ddr_d[7:0], dqm0
    - Slew slowest
    - Drive Strength 10 mA
CONTROL: DDR_IO_CTRL = 0x00000000
  * Bit 31: DDR_RESETn controlled by EMIF.
  * Bit 28 (mddr_sel) configured for SSTL, i.e. DDR2/DDR3/DDR3L operation.
CONTROL: VTP_CTRL = 0x00010167
  * VTP not disabled (expected in normal operation, but not DS0).
CONTROL: VREF_CTRL = 0x00000000
  * VREF supplied externally (typical).
CONTROL: DDR_CKE_CTRL = 0x00000001
  * CKE controlled by EMIF (normal/ungated operation).

karmliu

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