关于f28377sADC采样频率的设置

以下是我设置的单通道ADC采样，但是我不知道具体的采样频率是多少？我希望能达到5kHZ的采样频率；

我设置ADC的中断产生时机在转换后产生中断，意思是采样周期就是电压处理为转换结果的时间么？

我看到手册上说在12位模式下，内核需要10.5个ADCCLK才能将电压处理为转换结果，我的SYSCLK=5ns，设置ADCCLK 4分频，ADCCLK=SYSCLOCK/4=1.25ns，电压处理为转换结果=10.5*ADCCLK=13.125ns；而采集窗口=（ACQPS + 1）∙（SYSCLK）=75ns，我又看到采样窗会影响的是采样保持到转换结果的时间，可是明明比我算出来的13.125ns大很多啊？实在算不明白了，希望TI大神不吝赐教！

void ConfigureADC(void)
{
    EALLOW;
  
    AdcaRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to /4 决定ADCCLOCK，用于为转换器提供时钟，在12位模式下，内核需要10.5个ADCCLOCK才能将电压处理为转换结果
    AdcbRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to /4 ADCCLOCK=SYSCLOCK/4=1.25ns
    AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);//设置ADC的采样分辨率为12bit，单输入模式（区别于差分模式）
    AdcSetMode(ADC_ADCB, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);

    //
    //Set pulse positions to late
    //
    AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;//设置ADC的中断产生时机在转换后产生中断
    AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1;//ADC Interrupt Pulse Position.
                                         //0 Interrrupt pulse generation occurs at the end of the acquistion window
                                         //1 Interrupt pulse generation occurs at the end of the conversion, 1
                                         // cycle prior to the ADC result latching into its result register

    //
    //power up the ADCs
    //
    AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;   //给ADC上电，注意需要延时1ms左右等待上电完成
    AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;

    //
    //delay for 1ms to allow ADC time to power up
    //
    DELAY_US(1000);

    EDIS;
}

//
// SetupADCSoftware - Configure ADC SOC and acquisition window
//
void SetupADCSoftware(void)
{
    Uint16 acqps;

    //
    //determine minimum acquisition window (in SYSCLKS) based on resolution
    //
    if(ADC_RESOLUTION_12BIT == AdcaRegs.ADCCTL2.bit.RESOLUTION)
    {
        acqps = 14; //75ns

    else //resolution is 16-bit
    {
        acqps = 63; //320ns
    }

    //Select the channels to convert and end of conversion flag
  
    EALLOW;
    AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0x0E;  //SOC0 will convert pin ADCIN14  采样通道
    AdcaRegs.ADCSOC0CTL.bit.ACQPS = acqps; //sample window is 100 SYSCLK cycles采样窗会影响的是采样保持到转换结果的时间。
    AdcaRegs.ADCSOC1CTL.bit.CHSEL = 0x0E;  //SOC1 will convert pin ADCIN14  采样通道
    AdcaRegs.ADCSOC1CTL.bit.ACQPS = acqps; //sample window is 100 SYSCLK cycles
    AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 1; //end of SOC1 will set INT1 flag（这里一般配置为最后一个优先级的soc即可，注意要随时修改）
    AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1;   //enable INT1 flag（如果不配置这里，那么ADC采样完成后中断flag不会置位，所以必须配置为1）
    AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared
    //
    //ADCB
    //
    AdcbRegs.ADCSOC0CTL.bit.CHSEL = 0;  //SOC0 will convert pin B0
    AdcbRegs.ADCSOC0CTL.bit.ACQPS = acqps; //sample window is 100 SYSCLK cycles
    AdcbRegs.ADCSOC1CTL.bit.CHSEL = 0;  //SOC1 will convert pin B0
    AdcbRegs.ADCSOC1CTL.bit.ACQPS = acqps; //sample window is 100 SYSCLK cycles
    AdcbRegs.ADCINTSEL1N2.bit.INT1SEL = 1; //end of SOC1 will set INT1 flag
    AdcbRegs.ADCINTSEL1N2.bit.INT1E = 1;   //enable INT1 flag
    AdcbRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared
    EDIS;
}