Part Number: TLV320AIC3204 这是我的寄存器配置
MCLK=24.576MHZ,WCLK=3.072MHZ,BCLK=48KHZ,AIC3204处于主模式,给FPGA提供WCLK和BCLK
# 寄存器 写入数据
0x00,0x00 // Initialize to Page 0
0x01,0x01 // S/W Reset to initialize all registers
0x0b,0x81 // Power up NDAC divider with value 1 …
Other Parts Discussed in Thread: TDA4VM 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。 https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1553006/tda4vm-conversion-from-pth-to-onnx-after-training-yolox_s_lite-through…
Other Parts Discussed in Thread: ADC12DJ5200-SP 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。 https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1260214/adc12dj5200-sp-maximum-frequency-for-direct-di…
得到的回复:
Perhaps customer specs for setup and hold times, are referred to digital data output from SoC to TAS2564, meaning SDIN from TAS2564 perspective. There are similar setup and hold times called for SDIN in TAS2564 data sheet, and both are higher…
Other Parts Discussed in Thread: ADC34J45 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。 https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1367957/adc34j45-about-connection-between-analog-and-digital…