应该不会超过DDR3总宽，请看附件throughput performance文档。
5.6 Scenario 6: EDMA Transfer From Different CorePac L2 to DDR3 2656.Throughput Performance Guide for C66x KeyStone Devices (Rev. A).pdf
Fei wang你好：
关于R、C的配置在User Guide里面有详细的说明，我摘抄如下：
1. Determine the convergence length C = N*(K - 1).
2. Determine the number of sliding windows: Nsw= ceil(f/[(r + c)max - c]).
3. Determine the reliability length: R = m × ceil[f/(Nsw × m)].…
