Hello，
For any PLL requirement, I would recommend to use the TI Clock Tree Architect tool to generate your required clocks, which will recommend you the part for your clocks requirement. https://www.ti.com/tool/CLOCK-TREE-ARCHITECT
According to your requirement…
不能拆除，请看附件EVM板TRM文档上对FPGA的作用说明。
The FPGA (Xilinx XC3S200AN) controls the EVM power sequencing, reset mechanism, DSP boot mode configuration and clock initialization. The FPGA also provides the transformation of TDM Frame Synchronization signal and Reference…
Other Parts Discussed in Thread: UCD3138PSFBEVM-027 Using the UCD3138PSFBEVM-027.pdf
请问，UCD3138PSFBEVM-027开发板上的主电路用的是二极管钳位超前型移相全桥吗？
有文档说，滞后型损耗更小点，为什么会选用超前型？
如果我想改为在开发板的软硬件设计上，改为滞后型，是不是只要更改硬件设计，如改变变压器初级和谐振电感位置，而不用再更改固件，就可以实现滞后型了吧？
谢谢。
