Hi,
I followed your instructions: replaced the USB cable, added capacitor C7:A, and connected USB_GND to GND through the wire. I tried these three methods, but all failed in the end.
After the auxiliary power （12V 2A）was connected, JTAG was immediately…
Other Parts Discussed in Thread: CSD18531Q5A 请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。 https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1284781/lm25145-lm25145---mosfet-power-loss-calculation…
Other Parts Discussed in Thread: CSD18531Q5A 请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。 https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1284781/lm25145-lm25145---mosfet-power-loss-calculation…
Other Parts Discussed in Thread: CSD18531Q5A 请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。 https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1284781/lm25145-lm25145---mosfet-power-loss-calculation…
Hi,
The Formula is correct, its evaluation for the values used is a little off.
Kindly use the excel tool LM5163-LM5164DESIGN-CALC Calculation tool | TI.com to calculate Cout_min.
Higher capacitor value is chosen to have a good margin even after the DC bias…
First, could you please provide your schematic? Second, did you still see this behavior when you correctly connected the thermal pads? Leaving those pads unconnected could be the cause of the HO/LO behavior because GaN drivers are switching so quickly…
Part Number: BQ76952 The charge and discharge FETs arranged in series, when the charge FET is turn off(the CHG PIN is off ),the DSG PIN voltage is only 8V(P+/P- no load);But when we add a load at P+/P- (Like a 1M resistor),the DSG PIN voltage rise up…
请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。 尊敬的 Fusheng：
感谢您的更新。 从原理图中可以看出、有两个并联的电源块、即 PQ17和 PQ18、这应该没问题、但我会推荐以下链接中的应用手册、以了解有关并联 FET 的指南。 每个 FET 应具有自己的栅极电阻器、用于电流共享并防止两个并联 FET 之间出现栅极振荡。 该设计采用单个高侧和单个低侧栅极电阻器。 最好为每个 FET 将它们分别拆分为单独的电阻器。 开关节点波形上存在电压尖峰…
