Part Number: TDA4VH-Q1
你好,
TDA4VH开发板参考设计里SERDES1用于连接到PCIe x4 lane CONN.、SERDES0用于连接到PCIe x2 lane CONN.以及连接到USBC上。
1. SERDES1的参考时钟 SERDES1_REFCLK是接收时钟信号的,PCIE_REFCLK0_P/N_OUT是断开的(bom里0ohm电阻是DNI的);
2.SERDES0的参考时钟SERDES0_REFCLK是断开(bom里0ohm电阻是DNI的)的,PCIE_REFCLK1_P…
请看下面e2e工程师的回复。
Can you elaborate what do you mean by output here ?
Are you talking about compiled model artifacts binaries or some post processing output dump or anything else ?
Shine said:
2. How to transfer the output Models from Main Domain to MCU…
Part Number: TDA4VH-Q1
Hi Ti:
我们使用tda4vh 8.6的sdk,发现在linux sdk 9.0的driver里面,wave5驱动有一次提交是关于内存优化的,链接如下
https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/commit/drivers/media/platform/chips-media/wave5?h=ti-linux-6.1.y&id=994fd440867f78fd6a179096…
Part Number: TDA4VH-Q1
关于引脚之前的交流中知道了存在9个BANK,每个BANK16个引脚,如何分辨管脚属于哪一个BANK?如何分辨任意的两个引脚是否为同一个BANK?
In the previous communication about the pins, it was found that there are 9 BANKs, each with 16 pins. How can I distinguish which BANK the pins belong to…
Other Parts Discussed in Thread: DP83TG720S-Q1 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。 https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1301246/dp83tg720s-q1-how-to-implement-an-interrupt-when-link-down-on-dp83tg720s…