Hi,
Below is the schematic of EVM's VSET input structure. Please can you check and confirm if your customer has populated R11 resistor? By default is it not connected in EVM. But if it is connected the potentiometer R8 state will decide the VSET" voltage…
Below are the images of my setup:
The red wire is the sinewave output from a signal generator (settings are shown in the second image)
The black wire is the signal generator reference e.g. ground, which is connected to the EVM ground
The orange wire…
Hello,
The "GND" circuit here (using OPA1692) is intended to center the JFET input circuit in the middle of the 9V battery. It will effectively force the battery voltage (9V) to track GND to mid-supply (+/- 4.5 V) so the JFET circuitry has headroom…