你好,
你能提供你正在使用的MCLK、BCLK和WCLK吗?为了我的理解,我已经注释了你的登记簿,我也会把它放在这里。如果你能在测量失真和频率折叠时提供示波器(信号和时钟)的屏幕截图或图片,那也很好。
{0x36, 0x0f, 0x000},//reset first
{0x36, 0x00, 0x017}, #left line input channel volume, default value 0dB
{0x36, 0x01, 0x017}, #right line in
{0x36…
Okay, I understand. I think I missed providing some information—this is the schematic diagram of the inverting amplifier.
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I tried connecting an electrolytic capacitor in series between the input of the ADC and the output of the amplifier circuit…
Hi,
I am currently conducting lab 1. After debugging, the ADC is functioning normally, but there is no 0.5 pu output. The input is then sent out through this rectifier bridge. Could you please offer me some suggestions?
Part Number: TLV320AIC3101 咨询一下,TLV320AIC3101-EVM 外部输入CLK,SYNC,DATA,不使用MCLK,使用BCLK,使用官方软件配置芯片,有HPR声音有输出,CLK:2.048M,SYNC:8K,有声音输出,但不清晰,有杂音
配置命令如下:
Description= {PC Digital Audio (via USB) to DAC of AIC3107 with AC-MODEVM.? DAC analog out looped-back from…