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四层PCB,顶层和底层运放对称布局的干扰问题

Other Parts Discussed in Thread: OPA4228

这是四层板,差分采样电路。运放采用AD8692ARZ(8引脚),差分采样信号,采样时间为10us。板子的面积有限,目前是上下两层各一个运放,不知道这样布局需不需要考虑高频干扰的问题。

如果考虑,是不是上下层两个运放,交错比较好一些。