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At start of DSD decode, ADAC is set from PCM to DSD, and in that time, about 4V DC offset is arisen at OPAMP output as shown in Fig.1.
Why this DC offset happens ?
Software setting Problem ?
or the design defect of ADAC ?
也来看看 "断章取义" 的文字, 不过这段文字, 我在PCM1795手册 SLES248A –MAY 2009–REVISED MARCH 2015 上并没有找到. 不知道出自哪里?
Hello, do you mean the DC offset shift on the Lineout in the red cycle in your plot or the DC offset rising of the Opamp out in the green plot ?
