LMK04828: LMK04828时钟无输出问题

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我在论坛上找到了配置方法。我现在使用了新的配置参数，使用后现在DCLK_out没有输出，SDCLK_out输出sysref有输出时钟。还有PLL2也没有锁定。请问我现在的配置还有什么不合理的地方吗？

下面附上的新的配置txt和我的verilog代码。

R0 (INIT)	0x000090
R0	0x000000
R2	0x000200
R3	0x000306
R4	0x0004D0
R5	0x00055B
R6	0x000600
R12	0x000C51
R13	0x000D04
R256	0x01006A
R257	0x010155
R258	0x010255
R259	0x010301
R260	0x010422
R261	0x010500
R262	0x010672
R263	0x010766
R264	0x01086A
R265	0x010955
R266	0x010A55
R267	0x010B00
R268	0x010C22
R269	0x010D00
R270	0x010EF0
R271	0x010F66
R272	0x01106A
R273	0x011155
R274	0x011255
R275	0x011301
R276	0x011422
R277	0x011500
R278	0x011672
R279	0x011763
R280	0x01186A
R281	0x011955
R282	0x011A55
R283	0x011B01
R284	0x011C22
R285	0x011D00
R286	0x011E72
R287	0x011F66
R288	0x012074
R289	0x012155
R290	0x012255
R291	0x012301
R292	0x012422
R293	0x012500
R294	0x012670
R295	0x012766
R296	0x01286A
R297	0x012955
R298	0x012A55
R299	0x012B00
R300	0x012C22
R301	0x012D00
R302	0x012EF0
R303	0x012F66
R304	0x01306A
R305	0x013155
R306	0x013255
R307	0x013301
R308	0x013422
R309	0x013500
R310	0x013672
R311	0x013766
R312	0x013800
R313	0x013903
R314	0x013A00
R315	0x013B05
R316	0x013C00
R317	0x013D01
R318	0x013E03
R319	0x013F02
R320	0x014009
R321	0x014100
R322	0x014200
R323	0x014331
R324	0x0144FF
R325	0x01457F
R326	0x01461B
R327	0x01471A
R328	0x014802
R329	0x014902
R330	0x014A06
R331	0x014B26
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015011
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x01547D
R341	0x015500
R342	0x015601
R343	0x015700
R344	0x0158C0
R345	0x015900
R346	0x015A05
R347	0x015BDA
R348	0x015C20
R349	0x015D00
R350	0x015E00
R351	0x015F0B
R352	0x016000
R353	0x016104
R354	0x016244
R355	0x016300
R356	0x016400
R357	0x016532
R369	0x0171AA
R370	0x017202
R380	0x017C15
R381	0x017D33
R358	0x016600
R359	0x016700
R360	0x016832
R361	0x016959
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E13
R371	0x017300
R386	0x018200
R387	0x018300
R388	0x018400
R389	0x018500
R392	0x018800
R393	0x018900
R394	0x018A00
R395	0x018B00
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF53

下面是tcs文件

发不出来。

下面是verilog代码。

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2021/11/25 17:50:43
// Design Name: 
// Module Name: spi_top_ad9516
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module spi_top_lmk04832 # (
    parameter WIDTH      = 8'd24, 		
    parameter ADDR_WIDTH = 8'd16
)
(
	input              clk_5M              ,
	output             spi_csn             ,
	output             spi_clk             ,
	inout              spi_sdio            ,
	input              rst         	       ,
    output  wire[7 : 0]spi_data_back       ,
	input 		   	   vio_ctrl 	       ,
	input	[23:0]	   vio_data 	
    );

localparam REG_NUM            = 8'd143;


reg[WIDTH - 1: 0]  spi_data          ;
reg                spi_data_valid    ;
reg[7 : 0]         spi_data_cnt      ;
reg[3 : 0]         state             ;
wire               spi_busy          ;
reg                spi_done          ;
reg[4 : 0]         dly_cnt           ;
                                   
reg                vio_ctrl_d1       ;
reg                vio_ctrl_d2       ;
reg                vio_ctrl_d3       ;
                                   
reg                spi_busy_d1       ;
reg                spi_busy_d2       ;
reg                spi_busy_d3       ;
                                   
reg 		       configure_en_d1   ;
reg 		       configure_en_d2   ;
reg 		       configure_en_d3   ;
                                   
reg [23:0]         configure_data_d1 ;
reg [23:0]         configure_data_d2 ;
reg [23:0]         configure_data_d3 ;
                                   
wire               vio_ctrl_neg      ;
wire               spi_busy_neg      ;
//wire[7 : 0]        spi_data_back     ;
wire 		       configure_neg 	  ;

assign     vio_ctrl_neg  = !vio_ctrl_d2 && vio_ctrl_d3;
assign     spi_busy_neg  = !spi_busy_d2 && spi_busy_d3;
// assign     configure_neg = !configure_en_d2 && configure_en_d3;


always @ (posedge clk_5M) begin
	vio_ctrl_d1 <= vio_ctrl;
	vio_ctrl_d2 <= vio_ctrl_d1;
	vio_ctrl_d3 <= vio_ctrl_d2;
end

always @ (posedge clk_5M) begin
	spi_busy_d1 <= spi_busy;
	spi_busy_d2 <= spi_busy_d1;
	spi_busy_d3 <= spi_busy_d2;
end



wire [23:0]         Config_Param[142:0];

//Register Configuration Table for 04828

assign Config_Param[  0] = {16'h0000,8'h90};//soft reset
assign Config_Param[  1] = {16'h0000,8'h00};//写00三线SPI
assign Config_Param[  2] = {16'h0002,8'h00};//0x002-0x00d默认寄存器
assign Config_Param[  3] = {16'h0003,8'h06};
assign Config_Param[  4] = {16'h0004,8'hD0};
assign Config_Param[  5] = {16'h0005,8'h5B};
assign Config_Param[  6] = {16'h0006,8'h00};
assign Config_Param[  7] = {16'h000c,8'h51};
assign Config_Param[  8] = {16'h000d,8'h04};
assign Config_Param[  9] = {16'h0100,8'h6A};//DCLKout0;drive level;
assign Config_Param[ 10] = {16'h0101,8'h55};//digital delay
assign Config_Param[ 11] = {16'h0102,8'h55};
assign Config_Param[ 12] = {16'h0103,8'h01};//analog delay
assign Config_Param[ 13] = {16'h0104,8'h22};//half step;SYSREF output MUX;digital delay
assign Config_Param[ 14] = {16'h0105,8'h00};//analog delay;SYSREF
assign Config_Param[ 15] = {16'h0106,8'h72};//power down functions for the digital delay
assign Config_Param[ 16] = {16'h0107,8'h66};//output polarity
assign Config_Param[ 17] = {16'h0108,8'h6A};//drive level,divider values.
assign Config_Param[ 18] = {16'h0109,8'h55};//digital delay high;device clock outputs.
assign Config_Param[ 19] = {16'h010a,8'h55};//0x100-0x137配置输出
assign Config_Param[ 20] = {16'h010b,8'h00};
assign Config_Param[ 21] = {16'h010c,8'h22};
assign Config_Param[ 22] = {16'h010d,8'h00};
assign Config_Param[ 23] = {16'h010e,8'hF0};
assign Config_Param[ 24] = {16'h010f,8'h66};
assign Config_Param[ 25] = {16'h0110,8'h6A};
assign Config_Param[ 26] = {16'h0111,8'h55};
assign Config_Param[ 27] = {16'h0112,8'h55};
assign Config_Param[ 28] = {16'h0113,8'h01};
assign Config_Param[ 29] = {16'h0114,8'h22};
assign Config_Param[ 30] = {16'h0115,8'h00};
assign Config_Param[ 31] = {16'h0116,8'h72};
assign Config_Param[ 32] = {16'h0117,8'h63};
assign Config_Param[ 33] = {16'h0118,8'h6A};
assign Config_Param[ 34] = {16'h0119,8'h55};
assign Config_Param[ 35] = {16'h011a,8'h55};
assign Config_Param[ 36] = {16'h011b,8'h01};
assign Config_Param[ 37] = {16'h011c,8'h22};
assign Config_Param[ 38] = {16'h011d,8'h00};
assign Config_Param[ 39] = {16'h011e,8'h72};
assign Config_Param[ 40] = {16'h011f,8'h66};
assign Config_Param[ 41] = {16'h0120,8'h74};
assign Config_Param[ 42] = {16'h0121,8'h55};
assign Config_Param[ 43] = {16'h0122,8'h55};
assign Config_Param[ 44] = {16'h0123,8'h01};
assign Config_Param[ 45] = {16'h0124,8'h22};
assign Config_Param[ 46] = {16'h0125,8'h00};
assign Config_Param[ 47] = {16'h0126,8'h70};
assign Config_Param[ 48] = {16'h0127,8'h66};
assign Config_Param[ 49] = {16'h0128,8'h6A};
assign Config_Param[ 50] = {16'h0129,8'h55};
assign Config_Param[ 51] = {16'h012a,8'h55};
assign Config_Param[ 52] = {16'h012b,8'h00};
assign Config_Param[ 53] = {16'h012c,8'h22};
assign Config_Param[ 54] = {16'h012d,8'h00};
assign Config_Param[ 55] = {16'h012e,8'hF0};
assign Config_Param[ 56] = {16'h012f,8'h66};
assign Config_Param[ 57] = {16'h0130,8'h6A};
assign Config_Param[ 58] = {16'h0131,8'h55};
assign Config_Param[ 59] = {16'h0132,8'h55};
assign Config_Param[ 60] = {16'h0133,8'h01};
assign Config_Param[ 61] = {16'h0134,8'h22};//
assign Config_Param[ 62] = {16'h0135,8'h00};
assign Config_Param[ 63] = {16'h0136,8'h72};
assign Config_Param[ 64] = {16'h0137,8'h66};//输出极性
assign Config_Param[ 65] = {16'h0138,8'h00};//OSCont输出,and vco0 or vco1
assign Config_Param[ 66] = {16'h0139,8'h03};//SYSREF outputs
assign Config_Param[ 67] = {16'h013a,8'h00};//SYSREF output divider
assign Config_Param[ 68] = {16'h013b,8'h05};//SYSREF output divider
assign Config_Param[ 69] = {16'h013c,8'h00};//SYSREF digital delay value
assign Config_Param[ 70] = {16'h013d,8'h01};//SYSREF digital delay value
assign Config_Param[ 71] = {16'h013e,8'h03};//SYSREF pulses
assign Config_Param[ 72] = {16'h013f,8'h02};//feedback feature.//OSCIN,Feedback mux
assign Config_Param[ 73] = {16'h0140,8'h09};//OSCIN和SYSREF输入断电控制
assign Config_Param[ 74] = {16'h0141,8'h00};//SYSREF digital delay
assign Config_Param[ 75] = {16'h0142,8'h00};//number of dynamic digital delay
assign Config_Param[ 76] = {16'h0143,8'h31};//SYNC parameters
assign Config_Param[ 77] = {16'h0144,8'hFF};//sync
assign Config_Param[ 78] = {16'h0145,8'h7F};//默认
assign Config_Param[ 79] = {16'h0146,8'h1B};//CLKin enable and type controls.
assign Config_Param[ 80] = {16'h0147,8'h1A};//注意一下，选择PLL1输入
assign Config_Param[ 81] = {16'h0148,8'h02};//CLKin_SEL0 controls.
assign Config_Param[ 82] = {16'h0149,8'h02};//写02，支持回读寄存器
assign Config_Param[ 83] = {16'h014a,8'h06};//RESET pin
assign Config_Param[ 84] = {16'h014b,8'h26};//holdover functions
assign Config_Param[ 85] = {16'h014c,8'h00};
assign Config_Param[ 86] = {16'h014d,8'h00};
assign Config_Param[ 87] = {16'h014e,8'hC0};//DAC clock counter
assign Config_Param[ 88] = {16'h014f,8'h7F};//DAC when in tracked mode
assign Config_Param[ 89] = {16'h0150,8'h11};//switch events
assign Config_Param[ 90] = {16'h0151,8'h02};
assign Config_Param[ 91] = {16'h0152,8'h00};//PLL1 PDF before holdover is exited.
assign Config_Param[ 92] = {16'h0153,8'h00};//CLKin0 divide
assign Config_Param[ 93] = {16'h0154,8'h7D};//CLKin0 divide
assign Config_Param[ 94] = {16'h0155,8'h00};//CLKin1 R divider
assign Config_Param[ 95] = {16'h0156,8'h01};//CLKin1 R divider
assign Config_Param[ 96] = {16'h0157,8'h00};// CLKin2 R divider.
assign Config_Param[ 97] = {16'h0158,8'hC0};// CLKin2 R divider.
assign Config_Param[ 98] = {16'h0159,8'h00};//N divider value for PLL1.
assign Config_Param[ 99] = {16'h015a,8'h05};//N divider value for PLL1.
assign Config_Param[100] = {16'h015b,8'hDA};// PLL1 phase detector
assign Config_Param[101] = {16'h015c,8'h20};//PLL1 DLD counter
assign Config_Param[102] = {16'h015d,8'h00};//PLL1 DLD counter
assign Config_Param[103] = {16'h015e,8'h00};//PLL1 N and R delays.
assign Config_Param[104] = {16'h015f,8'h0B};//PLL1 LD pin.//SET00.STATUSLD2 USER
assign Config_Param[105] = {16'h0160,8'h00};//PLL2 R divider.
assign Config_Param[106] = {16'h0161,8'h04};
assign Config_Param[107] = {16'h0162,8'h44};//PLL2 functions.
assign Config_Param[108] = {16'h0163,8'h00};
assign Config_Param[109] = {16'h0164,8'h00};
assign Config_Param[110] = {16'h0165,8'h32};
assign Config_Param[111] = {16'h0171,8'hAA};//确保171号寄存器为AA
assign Config_Param[112] = {16'h0172,8'h02};//确保172号寄存器为02
assign Config_Param[113] = {16'h017c,8'h15};//确保lmk型号
assign Config_Param[114] = {16'h017d,8'h33};
assign Config_Param[115] = {16'h0166,8'h00};//PLL2频率校准
assign Config_Param[116] = {16'h0167,8'h00};//
assign Config_Param[117] = {16'h0168,8'h32};//
assign Config_Param[118] = {16'h0169,8'h59};//PLL2 phase detector.
assign Config_Param[119] = {16'h016a,8'h20};//PLL2 DLD counter
assign Config_Param[120] = {16'h016b,8'h00};
assign Config_Param[121] = {16'h016c,8'h00};//loop filter resistors.
assign Config_Param[122] = {16'h016d,8'h00};//loop filter capacitors
assign Config_Param[123] = {16'h016e,8'h13};//设置status_LD2引脚
assign Config_Param[124] = {16'h0173,8'h00};
assign Config_Param[125] = {16'h0182,8'h00};
assign Config_Param[126] = {16'h0183,8'h00};
assign Config_Param[127] = {16'h0184,8'h00};//回读
assign Config_Param[128] = {16'h0185,8'h00};//DAC for user readback.
assign Config_Param[129] = {16'h0188,8'h00};
assign Config_Param[130] = {16'h0189,8'h00};
assign Config_Param[131] = {16'h018a,8'h00};
assign Config_Param[132] = {16'h018b,8'h00};
assign Config_Param[133] = {16'h1ffd,8'h00};//spi_lock
assign Config_Param[134] = {16'h1ffe,8'h00};//
assign Config_Param[135] = {16'h1fff,8'h53};//写16'h53，SPI不锁定
//
assign Config_Param[136] = {16'h0144,8'h00};
assign Config_Param[137] = {16'h0143,8'h31};
assign Config_Param[138] = {16'h0143,8'h11};
assign Config_Param[139] = {16'h0144,8'hFF};
assign Config_Param[140] = {16'h0143,8'h11};
assign Config_Param[141] = {16'h0139,8'h03};




always @ (posedge clk_5M or posedge rst) begin
	if( rst ) begin
		spi_data       <= 24'd0;
		spi_data_valid <= 1'b0;
		spi_data_cnt   <= 8'd0;
		state          <= 4'd0;
		spi_done       <= 3'd0;
		dly_cnt        <= 5'd0;
	end else begin
		case( state )
			4'd0 : begin
				if( vio_ctrl_neg ) begin
					state <= 4'd1;
				end else if( spi_done ) begin
					state <= 4'd0;
				end else begin
					state <= 4'd3;
				end
			end
			4'd1 : begin
				if( spi_busy == 1'b0 ) begin
					spi_data       <= vio_data;
					spi_data_valid <= 1'b1;
					state          <= 4'd2;
				end else begin
					spi_data       <= vio_data;
					spi_data_valid <= 1'b0;
					state          <= 4'd1;
				end
			end
			
			4'd2 : begin
				spi_data_valid <= 1'b0;
				if( spi_busy_neg ) begin
					state <= 4'd0;
				end else begin
					state <= 4'd2;
				end
			end
			
			4'd3 : begin
				if( dly_cnt == 'd3) begin
						state          <= 4'd4;
						dly_cnt        <= 'd0;
						spi_data_valid <= 1'b1;
				end
                else begin
					state          <= 4'd3;
					dly_cnt        <= dly_cnt + 1;
					spi_data_valid <= 1'b0;
				end
                spi_data <= Config_Param[spi_data_cnt];
			end		
			4'd4 : begin
				spi_data_valid <= 1'b0;
				if( spi_busy_neg ) begin
					state <= 4'd5;
				end else begin
					state <= 4'd4;
				end
			end
			
			4'd5 : begin
				spi_data_cnt <= spi_data_cnt + 1;
				state        <= 4'd6;
			end
			
			4'd6 : begin
				if( spi_data_cnt == REG_NUM ) begin
					spi_done <= 1'b1;
					state    <= 4'd0;
				end else begin
					spi_done <= 1'b0;
					state    <= 4'd0;
				end
			end
		endcase
	end
end
wire spi_sdo;

wire spi_sdio_ctrl;					
	
spi_rw
	#(
		.WIDTH 		(WIDTH 		),
		.ADDR_WIDTH (ADDR_WIDTH ),//读写标志包含在地坿里靿
		.MSB_LSB 	(1'b1       )
	)
inst_spi_rw (
	.clk           ( clk_5M        ),
	.rst           ( rst            ),	
	.wr_data       ( spi_data       ),
	.wr_data_en    ( spi_data_valid ),								
	.spi_clk       ( spi_clk        ),
	.spi_csn       ( spi_csn        ),
	.spi_sdio_ctrl ( spi_sdio_ctrl  ),
	.spi_sdio      ( spi_sdio       ),	
	.spi_sdo       ( spi_sdo        ),
	.spi_data_back ( spi_data_back  ),
	.spi_busy      ( spi_busy       )	
); 
endmodule

请求您的帮助。我们领导要开除我了。

谢谢您的帮助，麻烦看一下我的最新回复。

我输出DCLK为500mhz，但是他只是是一个9mhz的信号。 输出SDCLK为500mhz，他显示输出了。 我这个DCLK为啥没有输出正确的时钟。

请求你们的帮助。