DATASHEET里这样写的：
CLOCK REQUIREMENTS
The CLK pin accepts a CMOS level clock input. The rising and falling edges of the externally applied convert command clock controls the various interstage conversions in the pipeline. Therefore, the duty cycle of the clock should be held at 50% with low jitter and fast rise-and-fall times of 2ns or less. This is particularly important when digitizing a highfrequency input and operating at the maximum sample rate.
Deviation from a 50% duty cycle will effectively shorten some of the interstage settling times, thus degrading the SNR and DNL performance.
我用25MHZ的有源晶振，但示波器观察是三角波，不满足上面的要求把，请问应该怎么产生？谢谢！
