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The high-speed modes (DRATE = 100, 101) are supported in high-speed LVDS interface mode only. The state of the LVDS pin and the SCLK_SEL are ignored. In these two modes, an on-chip PLL is used to multiply the input clock (CLK) by three, to be used for the serial interface. This high-speed clock enables all 23-bit output data to be shifted out at the high data rate. The DRDY pulse in this case is three serial clocks wide. The on-chip PLL can lock to input clocks ranging from 8MHz to 32MHz. To conserve power, the PLL is enabled only in the high-speed modes. After power up as well as after the CLK signal is issued, if the CLK frequency is changed, and when switching from low-speed mode to high-speed mode, the PLL needs at least tLPLLSTL to lock on and generate a proper LVDS serial shift clock. Switching among the high-speed modes does not require the user to wait for the PLL to lock. While the PLL is locking on, DOUT and SCLK are held low. After the PLL has locked on, the SCLK pin outputs a continuous clock that is three times the frequency of CLK.
