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关于ADS4129的10 clock cycles 延迟问题

上图中的ADC latency是10个时钟周期,那么在250msps时,是所有的采样都是延迟固定的10个时钟周期吗?是什么原因造成的这种延迟呢?

  • The device has several useful digital functions such as test patterns, gain, and offset correction. All of these functions require extra clock cycles for operation and increase the overall latency and power of the device.
    Alternately, the device has a low-latency mode in which the raw ADC output is routed to the output data pins with a latency of 10 clock cycles. In this mode, the digital functions are bypassed.