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是的,看这个时序, DVDD先上电, IOVDD和AVDD后上电，然后内部reset拉高,再经过2^18 clock周期和 129 data rate之后,DRDY由高到低,DOUT输出有效的数据．
Datasheet中Power supply中这部分的介绍中也有解释:
Following the CLK cycles, the data for 129 conversions are suppressed by the ADS1274/78 to allow output of fully-settled data. In SPI protocol, DRDY is held high during this interval. In frame-sync protocol, DOUT is forced to zero.
