16通道AFE5851问题

图片无法显示，时钟多少，什么提供，是否有测试过EVM板

图片能显示的啊，您打开后稍等也许网速慢刷的慢，板子的系统时钟是40MHZ，采样频率是20MHZ，由内部时钟提供，板子也有测试过，都通过了

Check the 5851 timing diagram.  We have 8 pair LVDS lines to handle 16CH data. Thus the data arrangment is not that simple. FCLK high level is CH N, FCLK low level is CH N+1

Thank you for your answer, but I have noticed that you mentioned the problems. I tested 16CH data, and through various test patterns on the board. I mentioned above is the test results of two channels in the case of an external signal generator. To sum up the problems I have mentioned, please give detailed answers.

您好，因为负责这个产品的工程师正在休假中，回复因此会有所延迟，非常感谢您的理解！！实在抱歉！