The internal seders PLL of the device is easy to lose lock. Please analyze the reason. ?
Adc09qj1300 adopts jesd204c 66/64b coding. At present, our project is 4lane interface, 4 channels AD, and the communication rate is 14.85Gbps. Through the ibert of fpga, it is found that the bit error rate is high. AD communicates with jesd284c of fpga, and finds that sync signal of phy is occasionally lost, and the output data is occasionally disconnected. If the rate is reduced to 9.9Gbps, the bit error rate will be much lower and the eye diagram will be much better, but the sync signal from phy at the fpga end will still be lost occasionally. Then the communication rate drops to 7.425Gbps. Looking at the BER and eye diagram through ibert of fpga, we find that the BER is higher. We often hang the chain. Looking at the status register 0x208 of ad, we find that the bit bit of Link_up is 0 occasionally, which indicates that the link of jesd204c on the AD side is unstable. Looking at the register 0x2c1, we find that spll is out of lock and Link is alarmed.
According to the reason, I reduced the communication rate, the bit error rate should be lower, and the communication quality will be better, but the pll of seders occasionally loses lock and the link is unstable.
