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我在调试ADC09QJ1300的过程中，发现建链不稳定的情况，配置AD的采样率为600M，4lane模式，7.425G的lane速率，发送prbs31给FPGA，FPGA的ibert检测信号误码率、眼图。
1.硬件连接
采用AD9517时钟芯片产生两路150MHz时钟，LVPECL电平，一路给ADC的clk+/-，一路给FPGA -zu4ev（xilinx Zynq UltraScale+ MPSOC ）的MGTHREFCLK+/-，AD的D0+/-~D3+/-共4路差分对与FPGA的gth口rx相连。
2.AD配置
AD输入时钟150MHz，经过cpll后产生600MHz的采样时钟。JESD配置为JMODE8模式，66/64b编码，4lane输出，线速率为600MHzX12bitX66/64=7.425Gbps，发送prbs31，配置寄存器如下
send_buf[0]=0x00;
send_buf[1]=0x00;
send_buf[2]=0xb0;//复位
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
while(recv_buf[2]!=0x01)
{
send_buf[0]=0x82;
send_buf[1]=0x70;
send_buf[2]=0x00;//等待初始化完成
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
}
send_buf[0]=0x00;
send_buf[1]=0x58;
send_buf[2]=0x81;//spi控制，PLL使能
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x02;
send_buf[1]=0x00;
send_buf[2]=0x00;//先关闭JESD
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x61;
send_buf[2]=0x00;//CAL_EN关闭
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x02;
send_buf[1]=0x01;
send_buf[2]=0x08;//配置JMODE 8
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x29;
send_buf[2]=0xb6;//开启sys_ref
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x29;
send_buf[2]=0xF6;//开启sys_ref 配置sysfre_window
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x2a;
send_buf[2]=0x00;//配置LVPECL
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x30;
send_buf[2]=0x00;//配置模拟信号Vpp采样最大值
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x31;
send_buf[2]=0xA0;//配置模拟信号Vpp采样最大值
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x5c;
send_buf[2]=0x01;//CPLL_RESET
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x3f;
send_buf[2]=0x4a;// CPLL_VCOCTRL1
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x3d;
send_buf[2]=0x0a;//0x06;//CPLL_FBDIV1
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x3e;
send_buf[2]=0x04;//0x08;//CPLL_FBDIV2
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x5d;
send_buf[2]=0x41;//VCO_CAL_CTRL
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x5c;
send_buf[2]=0x00;//CPLL_RESET 释放
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x48;
send_buf[2]=0x08;//预加重
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x02;
send_buf[1]=0x02;
send_buf[2]=0xff;//KM1 Register
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x02;
send_buf[1]=0x05;
send_buf[2]=0x0e;//测试模式选择 发送prbs31
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x61;
send_buf[2]=0x01;//CAL_EN
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x02;
send_buf[1]=0x00;
send_buf[2]=0x01;//打开JESD
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x6c;
send_buf[2]=0x00;//打开CAL_SOFT_TRIG
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
send_buf[0]=0x00;
send_buf[1]=0x6c;
send_buf[2]=0x01;//打开CAL_SOFT_TRIG
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
u8 result;
u32 addr=0x10000;
u32 wr_data;
u32 rd_data;
while(1)
{
send_buf[0]=0x82;
send_buf[1]=0x08;
send_buf[2]=0x00;//
XSpiPs_PolledTransfer(SpiInstancePtr, send_buf,recv_buf, 3);
usleep(5000);
result=recv_buf[2];
if((result & 0x44)!=0x44)//判断link up是否成功
{
i=0;
while(i==0);
}
}
3.FPGA配置
ibert的输入时钟为150MHz，4lane rx，设置线速率为7.425G，查看AD与FPGA的通信质量
4.现象如下
建链不稳定。通过读取AD的0x208寄存器，发现LINK_UP和SPLL_LOCKED两个bit位发生跳变，时而为1，时而为0，不知道具体原因
