ads1256EVM drdy不拉低

tao xin

Prodigy 20 points

Other Parts Discussed in Thread: ADS1256EVM-PDK

我用的是ads1256evm开发板，3脚接5V ，9脚3.3V,reset,CS用IO引脚控制的，上电以后，drdy一直是高的，

ADS_CS_LOW();
RESET_HIGH();
delay_us(100);
SPI_SendByte(0xfe);
delay_ms(10);
while(ADS_DRDY); 这个引脚一直是高的，不能拉低。

公司网站上的 ADS1256EVM-PDK Plugin Version 1.2.4 安装这个文件也不能下载，如果能下载，我可以用MMBO测试一下的。

9 年多前

0 user151383853 9 年多前

Guru 63421 points

DRDY 保持高有多个因素

DATA READY (DRDY)
The DRDY output is used as a status signal to indicate when conversion data is ready to be read. DRDY goes low when new conversion data is available. It is reset high when all 24 bits have been read back using Read Data (RDATA) or Read Data Continuous (RDATAC) command. It also goes high when the new conversion data is being updated. Do not retrieve during this update period as the data is invalid. If data is not retrieved, DRDY will only be high during the update time as shown in Figure 24.