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关于ethernet PHY DP83848M的 CLK_OUT引脚。

Other Parts Discussed in Thread: DP83848M

Dear TI 朋友们,

我打算用DP83848M, datasheet 只说CLK_OUT是一个时钟输出,没有更多的说明。

我的问题是:

1.  这个时钟是多少MHz?

2. 这个时钟是从哪里来? 是从数据中恢复的时钟 (像RXCLK)?还是来自于XTAL IN/OUT 脚? 我想是后者,不知对否?