DP83640-EVKRMII模式配置

您好，请参考这个帖子，e2e.ti.com/.../953508
问题和您的问题类似，两块DP83640 demo，一块做主，一块做从，里面给出了详细的配置；
1. Write 0x0000 to PHYCR2 (Page 0 Reg 0x1C) in Master DP83640 to enable CLK_OUT

2. Write 0x2000 to PHYCR2 (Page 0 Reg 0x1C) in Slave DP83640 to enable CLK_OUT and Enable Synchronous Ethernet.

3. Write 0x8019 to PTP_COC (Page 6 Reg 0x14) in both DP83640 , set CLK_OUT as 10MHz. Note that 0x19 is 25 decimal, to divide the 250 MHz clock by 25.

4. Write 0x0004 to PTP_CTL (Page 4 Reg 0x14) in both DP83640 , Enable PTP 1588.

5. Take 100 samples of the CLK_OUT phase error.

6. Enable the Event monitor and get the event timestamp:

6a. Write 0x1C0F to the PTP_EVNT register. This first write sets up a single event capture for CLK_OUT/GPIO12 with Event 7 (though any event may be used).

6b.Write 0x5C0F to the PTP_EVNT register. This second write does the same plus it enables the capture.

7. Read the PTP_ESTS register for bit 0 set. If not, wait and repeat step 6. Once bit 0 of PTP_ESTS has been set, determine the event timestamp length (1-4 16-bit words) by adding 1 to bits 7:6 of the PTP_ESTS value. Ensure the Event number is 7, (the PTP_ESTS value bits 4:2 equal 7). Ensure the event was a rising edge. This is indicated by the value of PTP_ESTS bit 5 equaling 1.

8. Read the PTP_EDATA register. The event timestamp is returned as follows:

Event nanoseconds bits 15:0
Event nanoseconds bits 29:16
Event seconds bits 15:0
Event seconds bits 31:16
9. Subtract (3 times the reference clock period + 11) from the timestamp; with the typical 8 ns reference clock period, this value is 35 ns. This corrects for the pin input delay and edge detection.

10. Calculate the phase error as (100 – (event timestamp mod 100)). If the result is equal to the clock period (100 ns in this case), the phase error is 0. If the phase error is within 10 ns of the clock period (91 – 99 ns in this case), set a flag “HighValue”. This is equivalent to a negative phase error of between -9 and -1 ns.

11. Average the phase error. If there are small positive and negative phase error samples, HighValue is set and a phase error sample is less than 10 ns, the clock period must be added to the sample in order for it to be averaged correctly:

If (HighValue & error[sample]<10) error[sample] += clkout_period
12. If the average phase error is greater than the clock period, subtract the clock period to get the final average phase error.

13. Calculate the correction value, which is the average phase error plus twice the reference clock period:

Correction = 2 * ref_period + avg_phase_error
14. . Do a step adjustment to the 1588 clock time:

Write the correction value to PTP_TDR.
Write PTP_STEP_CLK (0x8) to PTP_CTL.