Hello,
From the IC satasheet: Table 10. Power-Up Sequencing Constraints , t4(Startup time).
Q1: t4 meaning that PDB ahead of time to local IIC no more than 1ms ?
Q2: If t4 >1ms , what will be result ?
Thank you in advance!
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Hello,
From the IC satasheet: Table 10. Power-Up Sequencing Constraints , t4(Startup time).
Q1: t4 meaning that PDB ahead of time to local IIC no more than 1ms ?
Q2: If t4 >1ms , what will be result ?
Thank you in advance!
您好,关于您的两个问题,
1) 是的,PDB在VDDIO和VDD3电压起来之后,1ms时间内从低到高。等PDB 拉高稳定之后,再使用I2C通讯。
2)如果t4>1m没有遵循这个时序的话,首先芯片本身不会损坏,但是不能保证上电每个模块处于正常的状态,因此也就有可能会输出的数据无效,或者PLL不能正常锁存,或者工作一段时间不能稳定等等。