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CDCE62002配置问题以及锁定

Other Parts Discussed in Thread: CDCE62002, CDCM61004, CDCE62002EVM, CDCE62005

您好,我自己设计的PCB上现在用CDCM61004和CDCE62002两级PLL级联得到所需的500M时钟,CDCM61004为前级输出125M LVDS时钟作为CDCE62002的输入,输出需要500M LVDS时钟。目前的问题是,前级125M输出正常,在后级配置完CDCE62002的register0,1后,只能输出400M左右时钟,而且PLL 未锁定。配置为250M时钟只能输出200M左右,125M输出只能100M左右,而且都不能锁定。是寄存器配置不对吗?还是loop filter我只配置了internal,外部EXT_LP悬空未接,然后前级125M输出jitter大了造成不能锁定?现在很困惑,找不到问题在哪里,期盼尽快得到解答,非常感谢。