[参考译文] AM2634：使用 SysConfig 的 AM263x 外设时钟配置

您好、Bikash、  

当前、时钟配置基于 GEL。 连接到 R5时、GEL 将执行"Configure_PLLs_R5F_400_SYS_200_Clocks ()"、该函数调用多个函数以实现400MHz 的 R5时钟和200MHz 的 SYSCLK。  

在 OnTargetConnect()脚本中，我们有：

...

        //Configure PLLs
        Configure_Plls_R5F_400_SYS_200_Clocks();

        //Enable all peripheral clocks
        Configure_All_Peripheral_Clks();
    }else{
        GEL_TextOut("Warning !! None of the scripts executed in this mode\n");
    }
}

其中、"Configure_PLLs_R5F_400_SYS_200_Clocks ()"调用位于 "AM263x_PLL.GEL"中的"Program_Core_PLL（)"：

hotmenu Configure_Plls_R5F_400_SYS_200_Clocks()
{
    if(Enable_OnTarget_Connect == 1){
        Program_Core_PLL();
        Program_Per_PLL();
        Program_SYS_CLK_DIVBY2();
        // Switch R5SS and SYS_CLK to Core PLL, so that R5 run at 400MHz
        Program_R5F_SYS_CLK_SRC();
        GEL_TextOut("\n CLK Programmed R5F=400MHz and SYS_CLK=200MHz \n");
    }else{
        GEL_TextOut("Errrrr... Please Load Gel files\n");
    }
}

hotmenu Program_Core_PLL() 
{
    unsigned int val_pll_core_stat = 0;
    unsigned int val_pll_per_stat = 0;
    unsigned int val_hsdiv_clkout;   

    val_pll_core_stat = Read_MMR(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_STATUS);
    if((val_pll_core_stat & 0x00000400) != 0x00000400)
    {
        // N
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_M2NDIV, 9, 8, 0);
        //M2
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_M2NDIV, 1, 7, 16);
        
        //M
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_MN2DIV, 0x320, 12, 0); 
       
        //N2
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_MN2DIV, 0x0, 4, 16); 

        //SD divider of the PLL with the value of 0x8 to get the optimum jitter performance
        Write_MMR_Field(0x53200418, 8, 8,24);
        
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_CLKCTRL, 0,1, 23);        //Idle

        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_CLKCTRL, 0,1,0);  		//Soft Reset

        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_TENABLE, 1,1,0);          // PLL_CORE_TENABLE = 1;
        
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_CLKCTRL, 1,1,0);          //Soft Reset
        
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_TENABLE, 0,1,0);          // PLL_CORE_TENABLE = 0;
            
        Write_MMR(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_TENABLEDIV, 1);                 // PLL_CORE_TENABLEDIV = 1;
        Write_MMR(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_TENABLEDIV, 0);                 // PLL_CORE_TENABLEDIV = 0;
        
        do
        {     
            val_pll_core_stat = Read_MMR(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_STATUS);
        }while( ((val_pll_core_stat & 0x00000400) != 0x00000400) ) ;
        
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_HSDIVIDER_CLKOUT0, 0x4, 5, 0);//CLKOUT0
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_HSDIVIDER_CLKOUT1, 0x3, 5, 0);//CLKOUT1
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_HSDIVIDER_CLKOUT2, 0x4, 5, 0);//CLKOUT2
        
        
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_HSDIVIDER, 1,1,2);   // PLL_CORE_HSDIV_TENABLEDIV = 1;
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_HSDIVIDER, 0,1,2);   // PLL_CORE_HSDIV_TENABLEDIV = 0;
        
        
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_HSDIVIDER_CLKOUT0, 0x1, 1, 8);//CLKOUT0
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_HSDIVIDER_CLKOUT1, 0x1, 1, 8);//CLKOUT1
        Write_MMR_Field(MSS_TOP_RCM_U_BASE + MSS_TOP_RCM_PLL_CORE_HSDIVIDER_CLKOUT2, 0x1, 1, 8);//CLKOUT1
        
        GEL_TextOut("CORE PLL Configuration Complete \n");
    
    }
}

您可以通过修改 M 和 N 分频器以及 HSDIVIDER 值以输出所需的输出时钟值、以此作为示例使用此脚本。

 有关用于配置 PLL 的变量的详细信息、请参阅 TRM 的6.4.1.2模拟模块部分。 此外、有关如何配置内核 PLL 的更多详细说明、请参阅 第6.4.1.2.3.1.2节配置内核 PLL 的序列

最棒的

Daniel

TRM： AM263x Sitara 微控制器技术参考手册(修订版 B)链接(TI.com)