[参考译文] CC2640R2F：当 MRDY 未置位时、NPI 从器件发送 SPI 数据(后续)

我尝试了一种权变措施、其中涉及等待 MRDY 事件以设置 SPI 事务。

我在 npi_tl.h 顶部添加了一个 transportEnableWrite 函数(此处第7行：)

#elif defined(NPI_USE_SPI)
#define transportInit NPITLSPI_initializeTransport
#define transportRead NPITLSPI_readTransport
#define transportWrite NPITLSPI_writeTransport
#define transportStopTransfer NPITLSPI_stopTransfer
#define transportMrdyEvent NPITLSPI_handleMrdyEvent
#define transportEnableWrite NPITLSPI_enableWriteTransport
#endif

并在 NPIL_handleMrdyEvent 函数中从 NPI_tl.c 中调用它：

void NPITL_handleMrdyEvent(void)
{
    ICall_CSState key;
    key = ICall_enterCriticalSection();

    // Check to make sure this event is not occurring during the next packet
    // transmission
    if ( PIN_getInputValue(MRDY_PIN) == 0 ||
        (npiTxActive && mrdyPktStamp == txPktCount ) )
    {
        transportMrdyEvent();
        SRDY_ENABLE();

        if(npiTxActive)
        {
            //Set SPI count to correct length
            transportEnableWrite();
        }
    }

    ICall_leaveCriticalSection(key);
}

然后在 npi_tl_spi.c 中，我注释了来自 npitlspi_writeTransport ()的 spi_Transfer，而是将其移动到我的新函数 npitlspi_enableWriteTransport ()

// -----------------------------------------------------------------------------
//! \brief      This routine initializes and begins a SPI transaction
//!
//! \param[in]  len - Number of bytes to write.
//!
//! \return     uint8 - number of bytes written to transport
// -----------------------------------------------------------------------------
uint16 NPITLSPI_writeTransport(uint16 len)
{
    int16 i = 0;
    ICall_CSState key;

    key = ICall_enterCriticalSection();

    TransportTxBufLen = len + SPI_TX_FIELD_LEN;

    // Shift TX message two bytes to give room for SPI header
    for( i = ( TransportTxBufLen - 1 ) ; i >= 0 ; i-- )
    {
      TransportTxBuf[i + SPI_TX_HDR_LEN] = TransportTxBuf[i];
    }

    // Add header (including a zero padding byte required by the SPI driver)
    TransportTxBuf[SPI_TX_ZERO_PAD_INDEX] = 0x00;
    TransportTxBuf[SPI_TX_SOF_INDEX] = SPI_SOF;
    TransportTxBuf[SPI_TX_LEN_INDEX] = len;

    // Calculate and append FCS at end of Frame
    TransportTxBuf[TransportTxBufLen - 1] =
        NPITLSPI_calcFCS(&TransportTxBuf[SPI_TX_LEN_INDEX],len + 1);

    // Clear DMA Rx buffer and clear extra Tx buffer bytes to ensure clean buffer
    //    for next RX/TX
    memset(TransportRxBuf, 0, NPI_TL_BUF_SIZE);
    memset(&TransportTxBuf[TransportTxBufLen], 0, NPI_TL_BUF_SIZE - TransportTxBufLen);

    // set up the SPI Transaction
    // Count set to 0 to avoid sending data before master is ready in a shared
    // SPI bus configuration
    spiTransaction.count = NPI_TL_BUF_SIZE;
    spiTransaction.txBuf = TransportTxBuf;
    spiTransaction.rxBuf = TransportRxBuf;

//    // Check to see if transport is successful. If not, reset TxBufLen to allow
//    // another write to be processed
//    if( ! SPI_transfer(spiHandle, &spiTransaction) )
//    {
//      TransportTxBufLen = 0;
//    }

    ICall_leaveCriticalSection(key);

    return TransportTxBufLen;
}

// -----------------------------------------------------------------------------
//! \brief      This sets SPI TX count to the full buffer size. This is only
//!             called once the MRDY pin has gone low to prevent data TX when
//!             master is not ready.
//!
//! \return     void
// -----------------------------------------------------------------------------
void NPITLSPI_enableWriteTransport()
{
    ICall_CSState key;
    key = ICall_enterCriticalSection();

    // Check to see if transport is successful. If not, reset TxBufLen to allow
    // another write to be processed
    if( ! SPI_transfer(spiHandle, &spiTransaction) )
    {
      TransportTxBufLen = 0;
    }

    ICall_leaveCriticalSection(key);
}

当然、我们已将原型添加到 npi_tl_spi.h

// -----------------------------------------------------------------------------
//! \brief      This sets SPI TX count to the full buffer size. This is only
//!             called once the MRDY pin has gone low to prevent data TX when
//!             master is not ready.
//!
//! \return     void
// -----------------------------------------------------------------------------
void NPITLSPI_enableWriteTransport(void);

现在，当想要发送数据 时，从站似乎会降低 SRDY 的值，但现在它将等待 NPIL_handleMrdyEvent()，以便设置 SPI_Transfer，而不是在时钟开始切换时立即在 MISO 上发送数据。  这样、主器件就可以与第二个从器件模块通信、而不会使第一个模块引起数据冲突。

对于比我更熟悉代码的人、这似乎是对正常修改吗？  我已经运行了几个测试、现在两个模块似乎都按照正确的流量控制运行。

谢谢、Erik