This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/969499/cdce949-q1-scl-hysteresis
大家好、
我的客户想知道 I2C SCL 输入的迟滞值。
请支持。
此致、
您好、Hirai-San、
我们没有这些数据、但总的来说、这大约是0.1 x VDD。
