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https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/910081/cdclvp1216-input-clock-rise-time-requirement-to-archive-no-more-than-71fs-rms-jitter-specified-in-the-data-sheet
输入时钟上升时间要求、用于存档数据表中指定的不超过71fs 的 RMS 抖动。
数据表表中的最小输入压摆率指定为1.5V/ns、表6.5、6.6
此致、 通道
