This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/793583/cdclvp1204-whether-the-device-has-output-signal-duty-cycle-limit
大家好、
器件是否具有输出 信号占空比限制？ 谢谢。
