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器件型号：SN65DSI84工具/软件：
您好：
我正在使用 SN65DSI84 桥接芯片、通过 Raspberry Pi 计算模块 4S 驱动 AUO P370IVN02.2 面板。
奇怪的是：
在测试图形模式下、一切看起来都很好。 LVDS 时钟和数据线处于活动状态、面板显示内部图形。
但使用实际视频输入 (DSI) 时、只有 LVDS 时钟出来。 数据线保持非活动状态、即使我可以看到 DSI 时钟和数据位于输入端。
PLL 锁定正常。 我会附加我的 i2cdump 和 DTS 设置、以便能够准确地看到我正在使用的文件。
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/bcm2835.h>
/ {
compatible = "brcm,bcm2835";
/* PWM0 function */
fragment@0 {
target = <&gpio>;
__overlay__ {
pwm_pins: pwm_pins {
brcm,pins = <18>;
brcm,function = <BCM2835_FSEL_ALT5>; // PWM1_0
brcm,pull = <0>;
};
};
};
fragment@1 {
target = <&pwm>;
__overlay__ {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
assigned-clock-rates = <50000000>;
status = "okay";
};
};
fragment@2 {
target-path = "/";
__overlay__ {
backlight_lvds: backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 1000000 0>; // 1KHz
brightness-levels = <0 1000>;
num-interpolated-steps = <1000>;
default-brightness-level = <400>;
enable-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
};
panel: panel {
compatible = "panel-lvds";
backlight = <&backlight_lvds>;
label = "AUO:G156HAN";
dual-link;
width-mm = <904>;
height-mm = <254>;
data-mapping = "vesa-24";
panel-timing {
clock-frequency = <45000000>;
hactive = <1920>;
hsync-len = <162>;
hfront-porch = <80>;
hback-porch = <80>;
vactive = <540>;
vsync-len = <15>;
vfront-porch = <15>;
vback-porch = <15>;
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dual-lvds-odd-pixels;
panel_in_a: endpoint {
remote-endpoint = <&bridge_out_a>;
};
};
port@1 {
reg = <1>;
dual-lvds-even-pixels;
panel_in_b: endpoint {
remote-endpoint = <&bridge_out_b>;
};
};
};
};
};
};
fragment@3 {
target = <&i2c0if>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
bridge@2c {
compatible = "ti,sn65dsi84";
reg = <0x2c>;
vcc-supply = <&vcc_1v8>;
enable-gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_in: endpoint {
remote-endpoint = <&dsi_out>;
data-lanes = <1 2 3 4>;
};
};
port@2 {
reg = <2>;
bridge_out_a: endpoint {
remote-endpoint = <&panel_in_a>;
};
};
port@3 {
reg = <3>;
bridge_out_b: endpoint {
remote-endpoint = <&panel_in_b>;
};
};
};
};
};
};
fragment@4 {
target = <&dsi1>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port {
dsi_out: endpoint {
remote-endpoint = <&bridge_in>;
};
};
};
};
fragment@5 {
target = <&i2c0if>;
__overlay__ {
status = "okay";
};
};
fragment@6 {
target = <&i2c0mux>;
__overlay__ {
status = "disabled";
};
};
fragment@7 {
target-path = "/";
__overlay__ {
vcc_1v8: vcc_1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
};
};
};
No size specified (using byte-data access)
0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 35 38 49 53 44 20 20 20 01 00 83 28 00 01 00 00 58ISD ?.?(.?..
10: 26 00 32 00 00 00 00 00 4c 05 03 00 00 00 00 00 &.2.....L??.....
20: 80 07 00 00 1c 02 00 00 21 00 00 00 2c 00 00 00 ??..??..!...,...
30: 05 00 00 00 94 00 0f 00 50 00 02 00 00 00 00 00 ?...?.?.P.?.....
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
f0: 00 00 00 00 40 00 00 80 00 00 00 00 00 00 00 00 ....@..?........
任何建议都会很有帮助。 非常感谢！
