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https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1127646/sn74lvc1g175-ep-initial-value-of-q-output
当 CLR 引脚连接到 VCC 时、如果没有 CLK 边沿、Q 输出会发生什么情况？
此致
未知。 请参阅 [常见问题解答]锁存器件的默认输出是什么？ (触发器、锁存器、寄存器)
