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https://e2e.ti.com/support/logic-group/logic/f/logic-forum/879515/sn74hct244-what-happen-if-input-transition-violation
您好！
该器件的输入转换上升和下降时间规格为 dt / dv：最大500ns。
如果违反此规范、会发生什么情况？
它是否会损坏或出现故障？
此致、
猪排
请参阅 [常见问题解答]慢速或浮点输入如何影响 CMOS 器件？
