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https://e2e.ti.com/support/logic-group/logic/f/logic-forum/947607/sn74lvc14a-what-is-the-output-when-sn74lvc14a-input-is-actually-floating
大家好、
您能否告诉我 SN74LVC74A 输入是否允许悬空？ 为什么？
当 SN74LVC14A 输入实际悬空时、输出是什么？
谢谢你
云晶
CMOS 输入不得悬空。
当输入恰好浮动到高于开关阈值时、相应的输出为低电平。 当输入恰好浮动到低于开关阈值时、相应的输出为高电平。
您将获得击穿电流。 请参阅 [常见问题解答]慢速或浮点输入如何影响 CMOS 器件？
