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https://e2e.ti.com/support/logic-group/logic/f/logic-forum/1311046/sn74lvc1g32-q1-input-and-output-pin-impedance
大家好、
当 VCC = OFF 或处于 UVLO 状态时、您可以确认输入和输出引脚阻抗吗？
谢谢！
楚兴
没有 UVLO。
Ioff 规范确实描述了器件断电时 I/O 引脚的泄漏电流。
