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部件号：MSP430FR5994 主题中讨论的其他部件：MSP-EXP430FR5994
因此，我在MSP-EXP430FR5994上运行了一些代码，其中对ADC进行采样，并根据PWM以32Hz的速率闪烁光。 我还在使用printf函数的标志中有代码。 但是，我的代码每秒只打印大约2-3次，但PWM和指示灯仍以32Hz的速度闪烁。 我想知道这是否意味着PWM和ADC的操作不会因执行printf所需的计算能力而停止。 我还想知道FR5994上的打印频率是否有上限。
我使用的代码，以防任何人需要它：
#include <msp430.h>
#include <stdio.h>
int main(void)
{
WDTCTL = WDTPW | WDTHOLD; // Stop WDT
// GPIO Setup
P1OUT &= ~BIT0; // Clear LED to start
P1DIR |= BIT0 | BIT1 | BIT2;
P1SEL1 |= BIT3;
P1SEL0 |= BIT2 | BIT3 ; // Check p88-90_s for what the hell we're doing in the last 3 lines
// 1.2 set to TA1.1, 1.3 set to ADC input (A3)
PJSEL0 = BIT4 | BIT5; // For XT1? (p118_s)
// Disable the GPIO power-on default high-impedance mode to activate
// previously configured port settings
PM5CTL0 &= ~LOCKLPM5;
P1OUT |= BIT0;
// Clock System Setup
CSCTL0_H = CSKEY_H; // Unlock CS registers
CSCTL1 = DCOFSEL_0; // Set DCO to 1MHz
CSCTL2 = SELA__LFXTCLK | SELS__DCOCLK | SELM__DCOCLK;
CSCTL3 = DIVA__1 | DIVS__8 | DIVM__1; // Set all dividers
CSCTL4 &= ~LFXTOFF; // Something related to the 32kHz oscillator, idfk
do
{
CSCTL5 &= ~LFXTOFFG; // Clear XT1 fault flag
SFRIFG1 &= ~OFIFG;
} while (SFRIFG1 & OFIFG); // Test oscillator fault flag
ADC12CTL0 = ADC12SHT0_0 | ADC12ON; // Sampling time, S&H=4, ADC12 on [p893, CTL0 = control 0, SHT0_0 = sample & hold time, knowledge of register value from p88_s]
ADC12CTL1 = ADC12SHP | ADC12SHS_4 | ADC12CONSEQ_2; // Use TA1.1 to trigger, (SHP means using sample timer (p897), SHS means "sample-and-hold source select" (p895, p84_s)
// which selects which source is used to activate sampling (4 being TA1.1 because of p84_s), CONSEQ_2 = Conversion sequence select,
// 2 means repeated-single-channel which means a single channel is converted and sampled, memory gets overriden everytime (p880)
ADC12CTL2 |= ADC12RES_2; // 12-bit conversion results, p897
//ADC12CTL3 |= ADC12CSTARTADD_3; // Use MEM3/MCTL3, p898
ADC12MCTL0 = ADC12INCH_3 | ADC12EOS; // A3 ADC input select from INCH (p901), output to MEM0, Vref+ = AVCC, EOS = end of sequence, bit is activated when sequence ends (p876)
ADC12IER0 |= ADC12IE0; // Enable ADC interrupt [IER = interrupt enable, for IFG0 bit, which tells us when the sequence is complete]
ADC12CTL0 |= ADC12ENC | ADC12SC; // Start sampling/conversion
P1OUT = 0x01;
// Configure TimerA1.1 to periodically trigger the ADC12
TA1CCR0 = 3906-1; // PWM Period for TA1, 3905/125000
TA1CCTL1 = OUTMOD_3; // TACCR1 set/reset (Shape of set/reset in p652)
TA1CCR1 = 1953; // TACCR1 PWM Duty Cycle
TA1CTL = TASSEL__SMCLK | MC__UP; // ACLK, up mode
printf("122\n");
__bis_SR_register(LPM0_bits | GIE); // Enter LPM0, enable interrupts
//int memval = ADC12MEM0; // Memory stored in MEM0, because it was set from above.
//printf("%d\n", memval);
}
// ADC12 interrupt service routine
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=ADC12_B_VECTOR
__interrupt void ADC12ISR (void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(ADC12_B_VECTOR))) ADC12ISR (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(ADC12IV, ADC12IV__ADC12RDYIFG))
{
//Some flag conditions, more important than we might originally think
case ADC12IV__NONE: break; // Vector 0: No interrupt
case ADC12IV__ADC12OVIFG: break; // Vector 2: ADC12MEMx Overflow
case ADC12IV__ADC12TOVIFG: break; // Vector 4: Conversion time overflow
case ADC12IV__ADC12HIIFG: break; // Vector 6: ADC12BHI
case ADC12IV__ADC12LOIFG: break; // Vector 8: ADC12BLO
case ADC12IV__ADC12INIFG: break; // Vector 10: ADC12BIN
case ADC12IV__ADC12IFG0: // Vector 12: ADC12MEM0 Interrupt
if (ADC12MEM0 >= 0x7ff){ // ADC12MEM0 = A1 > 0.5AVcc?
P1OUT |= BIT0; // P1.0 = 1
}
else
P1OUT &= ~BIT0;{ // P1.0 = 0
}
int memval = ADC12MEM0; // Memory stored in MEM0, because it was set from above.
printf("Within flag 0.\n");
printf("%d\n", memval);
break;
case ADC12IV__ADC12IFG1: break; // Vector 14: ADC12MEM1
case ADC12IV__ADC12IFG2: break; // Vector 16: ADC12MEM2
case ADC12IV__ADC12IFG3: break; // Vector 18: ADC12MEM3
case ADC12IV__ADC12IFG4: break; // Vector 20: ADC12MEM4
case ADC12IV__ADC12IFG5: break; // Vector 22: ADC12MEM5
case ADC12IV__ADC12IFG6: break; // Vector 24: ADC12MEM6
case ADC12IV__ADC12IFG7: break; // Vector 26: ADC12MEM7
case ADC12IV__ADC12IFG8: break; // Vector 28: ADC12MEM8
case ADC12IV__ADC12IFG9: break; // Vector 30: ADC12MEM9
case ADC12IV__ADC12IFG10: break; // Vector 32: ADC12MEM10
case ADC12IV__ADC12IFG11: break; // Vector 34: ADC12MEM11
case ADC12IV__ADC12IFG12: break; // Vector 36: ADC12MEM12
case ADC12IV__ADC12IFG13: break; // Vector 38: ADC12MEM13
case ADC12IV__ADC12IFG14: break; // Vector 40: ADC12MEM14
case ADC12IV__ADC12IFG15: break; // Vector 42: ADC12MEM15
case ADC12IV__ADC12IFG16: break; // Vector 44: ADC12MEM16
case ADC12IV__ADC12IFG17: break; // Vector 46: ADC12MEM17
case ADC12IV__ADC12IFG18: break; // Vector 48: ADC12MEM18
case ADC12IV__ADC12IFG19: break; // Vector 50: ADC12MEM19
case ADC12IV__ADC12IFG20: break; // Vector 52: ADC12MEM20
case ADC12IV__ADC12IFG21: break; // Vector 54: ADC12MEM21
case ADC12IV__ADC12IFG22: break; // Vector 56: ADC12MEM22
case ADC12IV__ADC12IFG23: break; // Vector 58: ADC12MEM23
case ADC12IV__ADC12IFG24: break; // Vector 60: ADC12MEM24
case ADC12IV__ADC12IFG25: break; // Vector 62: ADC12MEM25
case ADC12IV__ADC12IFG26: break; // Vector 64: ADC12MEM26
case ADC12IV__ADC12IFG27: break; // Vector 66: ADC12MEM27
case ADC12IV__ADC12IFG28: break; // Vector 68: ADC12MEM28
case ADC12IV__ADC12IFG29: break; // Vector 70: ADC12MEM29
case ADC12IV__ADC12IFG30: break; // Vector 72: ADC12MEM30
case ADC12IV__ADC12IFG31: break; // Vector 74: ADC12MEM31
case ADC12IV__ADC12RDYIFG: break; // Vector 76: ADC12RDY
default: break;
}
}
