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[参考译文] MSP430FR5962:ADC:通道序列模式

Guru**** 2439560 points
Other Parts Discussed in Thread: MSP430F5529, MSP430FR5962

请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

https://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1054285/msp430fr5962-adc-sequence-of-channels-mode

器件型号:MSP430FR5962
主题中讨论的其他器件:MSP430F5529

尊敬的 TI 专家:

我们是否有任何与 通道序列模式相关的示例? 我正在尝试配置我的、但我无法获取输入。

//P1.5 - A5 - Pin 5
    P1SEL0 |= BIT5;
    P1SEL1 |= BIT5;

    //P3.1 - A13 - Pin 3
    P3SEL0 |= BIT1;
    P3SEL1 |= BIT1;

    // Configure ADC12
    ADC12CTL0 = ADC12SHT0_2 | ADC12ON | ADC12MSC;       //16 clock cycles sampling, ADC on, multiple sample.
    ADC12CTL1 = ADC12SHP | ADC12SSEL_3 | ADC12CONSEQ_1; //Pulse mode. ADCCLK = SMCLK. Sequence-of-Channels Mode autoscan.
    ADC12CTL2 = ADC12RES_2;         //12-bit conversion results
    ADC12CTL3 = ADC12CSTARTADD_1;

    // Configure ADC input channels
    ADC12MCTL1 = ADC12INCH_5 | ADC12VRSEL_0;   //A2 ADC input select; Vref=VCC=3.3V
    ADC12MCTL2 = ADC12INCH_13 | ADC12VRSEL_0 | ADC12EOS;   //A3 ADC input select; Vref=VCC; End-of-sequence

    ADC12CTL0 |= ADC12ENC | ADC12SC;


Here is my ADC ISR code:

#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = ADC12_B_VECTOR
__interrupt void ADC12_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(ADC12_B_VECTOR))) ADC12_ISR (void)
#else
#error Compiler not supported!
#endif
{
   switch (__even_in_range(ADC12IV, ADC12IV__ADC12RDYIFG))
   {
        case ADC12IV__NONE:        break;   // Vector  0:  No interrupt
        case ADC12IV__ADC12OVIFG:  break;   // Vector  2:  ADC12MEMx Overflow
        case ADC12IV__ADC12TOVIFG: break;   // Vector  4:  Conversion time overflow
        case ADC12IV__ADC12HIIFG:  break;   // Vector  6:  ADC12BHI
        case ADC12IV__ADC12LOIFG:  break;   // Vector  8:  ADC12BLO
        case ADC12IV__ADC12INIFG:  break;   // Vector 10:  ADC12BIN
        case ADC12IV__ADC12IFG0:   break;   // Vector 12:  ADC12MEM0
        case ADC12IV__ADC12IFG1:
            var1 = ADC12MEM0;
        
        break;   // Vector 14:  ADC12MEM1
        case ADC12IV__ADC12IFG2:
            var2 = ADC12MEM1;
        
        break;   // Vector 16:  ADC12MEM2
        case ADC12IV__ADC12IFG3:   break;   // Vector 18:  ADC12MEM3
        case ADC12IV__ADC12IFG4:   break;   // Vector 20:  ADC12MEM4
        case ADC12IV__ADC12IFG5:   break;   // Vector 22:  ADC12MEM5
        case ADC12IV__ADC12IFG6:   break;   // Vector 24:  ADC12MEM6
        case ADC12IV__ADC12IFG7:   break;   // Vector 26:  ADC12MEM7
        case ADC12IV__ADC12IFG8:   break;   // Vector 28:  ADC12MEM8
        case ADC12IV__ADC12IFG9:   break;   // Vector 30:  ADC12MEM9
        case ADC12IV__ADC12IFG10:  break;   // Vector 32:  ADC12MEM10
        case ADC12IV__ADC12IFG11:  break;   // Vector 34:  ADC12MEM11
        case ADC12IV__ADC12IFG12:  break;   // Vector 36:  ADC12MEM12
        case ADC12IV__ADC12IFG13:  break;   // Vector 38:  ADC12MEM13
        case ADC12IV__ADC12IFG14:  break;   // Vector 40:  ADC12MEM14
        case ADC12IV__ADC12IFG15:  break;   // Vector 42:  ADC12MEM15
        case ADC12IV__ADC12IFG16:  break;   // Vector 44:  ADC12MEM16
        case ADC12IV__ADC12IFG17:  break;   // Vector 46:  ADC12MEM17
        case ADC12IV__ADC12IFG18:  break;   // Vector 48:  ADC12MEM18
        case ADC12IV__ADC12IFG19:  break;   // Vector 50:  ADC12MEM19
        case ADC12IV__ADC12IFG20:  break;   // Vector 52:  ADC12MEM20
        case ADC12IV__ADC12IFG21:  break;   // Vector 54:  ADC12MEM21
        case ADC12IV__ADC12IFG22:  break;   // Vector 56:  ADC12MEM22
        case ADC12IV__ADC12IFG23:  break;   // Vector 58:  ADC12MEM23
        case ADC12IV__ADC12IFG24:  break;   // Vector 60:  ADC12MEM24
        case ADC12IV__ADC12IFG25:  break;   // Vector 62:  ADC12MEM25
        case ADC12IV__ADC12IFG26:  break;   // Vector 64:  ADC12MEM26
        case ADC12IV__ADC12IFG27:  break;   // Vector 66:  ADC12MEM27
        case ADC12IV__ADC12IFG28:  break;   // Vector 68:  ADC12MEM28
        case ADC12IV__ADC12IFG29:  break;   // Vector 70:  ADC12MEM29
        case ADC12IV__ADC12IFG30:  break;   // Vector 72:  ADC12MEM30
        case ADC12IV__ADC12IFG31:  break;   // Vector 74:  ADC12MEM31
        case ADC12IV__ADC12RDYIFG: break;   // Vector 76:  ADC12RDY
        default: break;
   }


我看不到任何 ADC12MEMx 寄存器值正在更新。 有人能指出我做了什么错吗? 配置是否有问题或其他问题? 
请尽快答复我将不胜感激、因为我已经尝试了很多、并且在 ADC12MEMx 寄存器中找不到任何输入。 即使没有示例
由 TI 提供
那么、我很难弄清楚我做了什么错了?

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您好、Manish Thakur、

    我们在 MSP430F5529器件中确实有这方面的示例、它应该有助于详细说明通道序列模式的示例、并且它还使用与 MSP430FR5962器件相同的模块 ADC12。 此示例可在此处找到 MSP430F552x 演示- ADC12、转换序列(非重复)。 请记住、这适用于 MSP430F5529、因此它不会直接与您的器件配合使用、但会遵循相同的过程。

    我建议查看此示例、如果您有任何其他问题、请告诉我。

    此致、

    Luke

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    您有一个 ISR、但我看不到您在哪里启用任何中断。 (ADC12IE1和 ADC12IE2)

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    感谢 David、我3天前就已经解决了这个问题