[参考译文] MSP430F2619S-HT：MSP430F2619S-HT 如何与外部时钟信号配合使用

你(们)好，Kejun

首先、请检查 XT2OF 位以查看是否存在任何故障。

第二、尝试使用内部时钟源来确定是否可以正确输出 MCLK。

你好、Gary Gao

我修改下面的代码

   BCSCTL3 = XT2S_3；      //选择外部数字时钟
   BCSCTL1 &=~XT2OFF；      //XT2OFF 为0
   BCSCTL2 = DIVM_0 + DIVS_0；   //MCLK 分频器为1、SMCLK 分频器为1
   操作
   ｛
      __DELAY_CYCLES (100)；
      ClrWdt ()；
   }while (XT2OF =( BCSCTL3 & XT2OF))；

但我仍然看不到 SMCLK 引脚上的输出时钟信号、UART 模块不工作(选择 DCO 模块时工作)、

如何知道时钟从 DCO 切换到外部数字时钟信号是否成功？

王克拉克

你(们)好，Kejun

您似乎尚未将 SELMx 位设置为0x10、以选择 XT2作为 MCLK 的时钟源。

您好、Gary

我将 SELMx 位设置为0x10、信号频率来自 MCLK 为1.1MHZ、而不是8MHZ。

我现在不关心 MCLK、因为 我为器件提供了一个独立的时钟。 我只关心它可以与外部时钟信号配合使用、它只能与 DCO 时钟信号配合使用。

请告诉我我有什么问题。

您可以尝试使用 XTN 引脚8、该引脚可与我已验证的以下代码配合使用  

#include <msp430.h>

int main(void)
{
    volatile unsigned int i;
  WDTCTL = WDTPW + WDTHOLD;                 // Stop Watchdog Timer
  if (CALBC1_8MHZ==0xFF)                    // If calibration constant erased
  {
    while(1);                               // do not load, trap CPU!!
  }

  __bic_SR_register(OSCOFF); // enable LFXT1 oscillator

  BCSCTL1 |= XT2OFF + XTS; // LFXT1CLK is High Frequency
  BCSCTL3 |= LFXT1S0 + LFXT1S1;// Digital external 0.4- to 16-MHz clock source
  BCSCTL3 &= ~(XCAP0 + XCAP1);
  do // wait for oscillator to stablise
  {
  IFG1 &= ~OFIFG; // clear flag
  // do a delay of at least 50uS
  i = 0xFF;
  while (i > 0) i--;
  }
  while ((IFG1 & OFIFG) != 0);// repeat until flag remains cleared
  BCSCTL2 |= SELM1 + SELM0; // MCLK Source Select 3: LFXTCLK




  P5DIR |= 0x78;                            // P5.6,5,4,3 outputs
  P5SEL |= 0x70;                            // P5.6,5,4 options

  while (1)                                 // 10 MCLK cycle loop
  {
    P5OUT |= 0x08;                          // P5.3 = 1
    i = 50000;                              // Delay
    do (i--);
    while (i != 0);
    P5OUT &= ~0x08;                         // P5.3 = 0
    i = 50000;                              // Delay
    do (i--);
    while (i != 0);
  }
}

我也无法使用 XT2、并尝试在此处找到原因。

你(们)好、Gary

感谢你的帮助。

您的代码解决了外部时钟仅来自 MCLK 的问题、我的项目代码仍然无法正常工作、它的工作取决于 SMCLK、例如 UART、SPI 等。 CPU 如何处理与 DCO 时钟信号一样的外部时钟信号？

Clark

如果您想配置 SMCLK、是否已将 SELS 设置为1？ 您 可以为 SMCLK 选择外部时钟

你(们)好、Gary

我尝试了你所说的所有位置、以及手册中描述的所有位置。 不管用。

我的代码在 DCO 上运行得很好、我希望它也能在外部时钟上运行。 如果您能够确定我的

您可以咨询一些经验丰富的工程师。 我不相信任何人都不能解决这个问题。

Clark

你(们)好、Gary

我尝试了你所说的所有位置、以及手册中描述的所有位置。 不管用。

我的代码在 DCO 上运行得很好、我希望它也能在外部时钟上运行。 如果您能够确定我的

您可以咨询一些经验丰富的工程师。 我不相信任何人都不能解决这个问题。

Clark

你(们)好，Kejun

我已经创建了一个代码来使 XT2与 MCLK 和 SMCLK 一起工作。 您可以尝试它。(使其自由运行、不要使其处于调试模式)

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 *******************************************************************************
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 *                       MSP430 CODE EXAMPLE DISCLAIMER
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//******************************************************************************
//  MSP430x26x Demo - Basic Clock, Output Buffered SMCLK, ACLK and MCLK/10
//
//  Description: Buffer ACLK on P5.6, SMCLK(DCO) on P5.5, MCLK on P5.4 and
//  MCLK/10 on P5.3.
//  ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = CALxxx_8MHZ = 8MHz
//  //* External watch crystal on XIN XOUT is required for ACLK *//
//
//            MSP430F261x/241x
//             -----------------
//         /|\|              XIN|-
//          | |                 | 32kHz
//          --|RST          XOUT|-
//            |                 |
//            |             P5.6|-->ACLK = 32kHz
//            |             P5.5|-->SMCLK = 8MHz
//            |             P5.4|-->MCLK = DCO
//            |             P5.3|-->MCLK/10
//
//  B. Nisarga
//  Texas Instruments Inc.
//  September 2007
//  Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.42A
//******************************************************************************
#include <msp430.h>

int main(void)
{
    volatile unsigned int i;
  WDTCTL = WDTPW + WDTHOLD;                 // Stop Watchdog Timer

  P5DIR |= BIT4|BIT5|BIT3;                            // P5.6,5,4,3 outputs
  P5SEL |= BIT4|BIT5;                            // P5.6,5,4 options

  __bic_SR_register(OSCOFF); // enable LFXT1 oscillator

  BCSCTL1 &= ~XT2OFF; // XT2 ON
  BCSCTL3 |= XT2S_3;// Digital external 0.4- to 16-MHz clock source
  BCSCTL3 &= ~XT2OF;
//  P5OUT |= BIT3;                          // P5.3 = 1
  do // wait for oscillator to stablise
  {
  IFG1 &= ~OFIFG; // clear flag
  // do a delay of at least 50uS
  i = 0xFF;
  while (i > 0) i--;
  }
  while ((IFG1 & OFIFG) != 0);// repeat until flag remains cleared
//  P5OUT &= ~BIT3;                         // P5.3 = 0
  do
  {
      __delay_cycles( 100 );
  }while( XT2OF ==( BCSCTL3 & XT2OF) );

  BCSCTL2 |= SELM1|SELS; // MCLK Source Select 3: LFXTCLK
//  P5OUT |= BIT3;                          // P5.3 = 1


  while (1)                                 // 10 MCLK cycle loop
  {
    P5OUT |= BIT3;                          // P5.3 = 1
    i = 50000;                              // Delay
    do (i--);
    while (i != 0);
    P5OUT &= ~BIT3;                         // P5.3 = 0
    i = 50000;                              // Delay
    do (i--);
    while (i != 0);
  }
}

下面是波形捕获

e2e.ti.com/.../XT2_5F00_G.sal