你(们)好
我叫 Dung。
我有 MSP430i2041 EVM 1电压(990K-2.4K - 220VAC 最大250V)、3电流(CT 1000.1、R = 6.8R 最大80A)的项目、我的设计采用相同 的 TIDM-3OUTSMTSTRP 并使用 CT、不包括继电器。
我有一些问题。 创建项目时 EMDC 上的电流、为什么 TI 计算 器的电流值约为实际值。
当我通过 EMDC 为 MSP430i2041使用套件 MSP430F5529LP 进行校准时、如果仅将3个 CT 连接到 EVM、则可以将结果读取到 EMDC、当 我将1V 3C 连接到 EVM 时、它无法连接到 EMDC。 我不知道为什么(我 不使用 MSP-ISO)。
请注意不要使用 MSP-ISO。 如果 AC 线路被接至电路板接地而不是 AC 中性点、并且您没有使用 MSP-ISO、那么您的 PC 可能会被损坏、并且您可能会感到震惊。
您说的是、当您将交流电压连接到电路板时、通信会停止？ 这可能是电源问题。 电路板是如何供电的？ 电池？ 交流/直流电源？ F5529 LPTM 确保没有电源冲突。
确保在对任何引脚施加电压之前或期间为电路板供电(例如、连接传感器、连接 UART 引脚)。
[引用 userid="466056" URL"~/support/microcontrollers/msp430/f/msp-low-power-microcontroller-forum/983896/msp430i2041-msp430i2041-with-emdc-and-ccs-and-read-result-over-i2c/3637745 #3637745"] EVM 1电压(990K-2.4k - 220VAC 最大250V)、3电流(CT 1000.1、Rshun=6.8R 最大80A)、我的设计采用相同 的 TIDM-3OUTSMTSTRP 并使用 CT、不包括继电器。[/quot]我在 EMDC 中创建了同一个项目、并且连接到 i20xx 以查看结果或校准电路板时没有遇到任何问题。
下面是我这边的一些屏幕截图。
此致、
James
您的项目与我的项目相同运行。
[引用 userid="216616" URL"~/support/microcontrollers/msp430/f/msp-low-power-microcontroller-forum/983896/msp430i2041-msp430i2041-with-emdc-and-ccs-and-read-result-over-i2c/3638273 #3638273)]您说过、将交流电压连接到电路板时、通信会停止？ 这可能是电源问题。 电路板是如何供电的？ 电池？ 交流/直流电源？ F5529 LPTM 确保没有电源冲突。[/报价]我已经使用5529LP 和交流/直流电源、交流/直流模块以及相同的 TIDM-3OUTSMTSTRP 进行了电源测试。 我已小心地将 Neutral 连接到 EVM 的0V。 您能否在 TIDM-3OUTSMTSTRP 上测试校准帮助。 您的连接是什么？
当我校准时、我将 TX、RX、GND 连接到5529LP 板的 P3.4、P3.3和 GND。 不施加电压时的数据结果。
如果我向 EVM 施加电压、 我等待5分钟、数据不更新。
你(们)好 James。
[引用 userid="216616" URL"~/support/microcontrollers/msp430/f/msp-low-power-microcontroller-forum/983896/msp430i2041-msp430i2041-with-emdc-and-ccs-and-read-result-over-i2c/3666989 #3666989"]我很抱歉，但我不理解这一点。当 我在模式1V 3 CT 中使用所有参数(0x80-0x8B)创建新的项目 EVM 时、数据结果可以在交流电压未连接时与 EMDC 连接。 当我将交流电压连接到 EVM =>无法读取由 EMDC 校准的结果。
如果我使用 VRMS、IRMS、Vpeak、IPEAK、有功功率 能量功率模式1V 3 CT、我可以通过 EMDC 校准 EVM。
[引用 userid="216616" URL"~/support/microcontrollers/msp430/f/msp-low-power-microcontroller-forum/983896/msp430i2041-msp430i2041-with-emdc-and-ccs-and-read-result-over-i2c/3666989 #3666989">我不确定 Arduino 代码。 也许您可以将其发布在 Arduino 论坛上。 我还建议在 i20xx 上仅使用 TI Resource Explorer 中提供的 I2C 代码示例中的一个示例以及虚拟数据、以使 I2C 通信与 EMDC 项目分开工作。 然后、您可以在 EMDC 项目工作时将 I2C 代码集成到该项目中。您能否向我发送示例项目：MSP430F5529LP 与 EVM MSP430i2041之间的 I2C 通信。 通过 I2C 5529LP 读取结果后 、通过 UART 将数据调试发送到 PC。 我希望测试 I2C 读取数据在 MSP430Fxx 中正常。 请帮帮我。
我的项目需要通过 Wifi 互联网将数据发送到服务器。
非常感谢。
你(们)好 James。
我用 f5529编写代码。 我的项目 通过 I2C 读取 evmi2041 (多器件)并通过 UART 发送到 PC、现在我连接了一个器件 EVM、但数据结果不正确。 请与我联系
//******************************************************************************
// MSP430F552x Demo - USCI_B0, I2C Master multiple byte TX/RX
//
// Description: I2C master communicates to I2C slave sending and receiving
// messages of different length. I2C master will enter LPM0 mode
// while waiting for the messages to be sent/receiving using I2C interrupt.
// ACLK = NA, MCLK = SMCLK = DCO 16MHz.
//
// /|\ /|\
// MSP430F5529 4.7k |
// ----------------- | 4.7k
// /|\ | P3.1|---+---|-- I2C Clock (UCB0SCL)
// | | | |
// ---|RST P3.0|-------+-- I2C Data (UCB0SDA)
// | |
// | P3.3|-------+-- UART TX (UCA0 TXD)
// | |
// | P3.4|-------+-- UART RX (UCA0 RXD)
// | |
// | |
//
// Texas Instruments Inc.
// June 2019
// Built with CCS V9.x
//******************************************************************************
#include <msp430.h>
#include <stdint.h>
#include <stdbool.h>
char update;
//******************************************************************************
// UART Initialization *********************************************************
//******************************************************************************
#define SMCLK_11500 0
#define SMCLK_9600 1
#define ACLK_9600 2
#define UART_MODE SMCLK_115200
const char hex_digits[] = "0123456789ABCDEF";
void initUART()
{
// Configure USCI_A0 for UART mode
UCA0CTLW0 = UCSWRST; // Put eUSCI in reset
#if UART_MODE == SMCLK_115200
UCA0CTLW0 |= UCSSEL__SMCLK; // CLK = SMCLK
// Baud Rate calculation
// 16000000/(16*115200) = 8.6805
// Fractional portion = 0.6805
// Use Table 24-5 in Family User Guide
UCA0BR0 = 8; // 16000000/16/9600
UCA0BR1 = 0x00;
UCA0MCTL |= UCOS16 | UCBRF_11 | UCBRS_0;
#elif UART_MODE == SMCLK_9600
UCA0CTLW0 |= UCSSEL__SMCLK; // CLK = SMCLK
// Baud Rate calculation
// 16000000/(16*9600) = 104.1667
// Fractional portion = 0.1667
// Use Table 24-5 in Family User Guide
UCA0BR0 = 104; // 16000000/16/9600
UCA0BR1 = 0x00;
UCA0MCTL |= UCOS16 | UCBRF_3 | UCBRS_0;
#elif UART_MODE == ACLK_9600
UCA0CTLW0 |= UCSSEL__ACLK; // CLK = ACLK
// Baud Rate calculation
// 32768/(9600) = 3.4133
// Fractional portion = 0.4133
// Use Table 24-5 in Family User Guide
UCA0BR0 = 3; // 32768/9600
UCA0BR1 = 0x00;
UCA0MCTL |= UCBRS_3; //0x0300 is UCBRSx = 0x03
#else
# error "Please specify baud rate to 115200 or 9600"
#endif
UCA0CTLW0 &= ~UCSWRST; // Initialize eUSCI
UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt
}
//******************************************************************************
// Device Initialization *******************************************************
//******************************************************************************
void putcUART(uint8_t data)
{
while (!(UCA0IFG & UCTXIFG)); // USCI_A0 TX buffer ready?
UCA0TXBUF = data; // TX -> RXed character
}
void putsUART(uint8_t *data)
{
while (*data)
{
putcUART(*data);
data++;
}
}
void putHexUART(uint8_t c)
{ //uint8_t c;
putcUART(hex_digits[c >> 4]);
putcUART(hex_digits[c & 15]);
}
void putsHexPC(uint8_t *buff, uint8_t len)
{
uint8_t i;
for(i=0;i<len;i++) {
putHexUART(buff[i]);
putcUART(' ');
}
}
//******************************************************************************
// Example Commands ************************************************************
//******************************************************************************
#define SLAVE_ADDR 0x0A
#define MAX_BUFFER_SIZE 50
// CMD 0x01 = Configure Mode
#define CMD_01_MASTER 0x01
// send 2 bytes of payload
#define CMD_01_LENGTH 2
// Payload[0] = 0x01: Write, [1] = 0x01: Active
uint8_t MasterCMD01Payload [CMD_01_LENGTH] = { 0x01, 0x01};
#define RESPONSE_SLAVE_LENGTH 15
//******************************************************************************
// General I2C State Machine ***************************************************
//******************************************************************************
typedef enum I2C_ModeEnum{
IDLE_MODE,
NACK_MODE,
TX_DATA_MODE,
RX_DATA_MODE,
TIMEOUT_MODE,
ERROR_MODE
} I2C_Mode;
/* Used to track the state of the software state machine*/
I2C_Mode MasterMode = IDLE_MODE;
/* ReceiveBuffer: Buffer used to receive data in the ISR
* RXByteCtr: Number of bytes left to receive
* ReceiveIndex: The index of the next byte to be received in ReceiveBuffer
* TransmitBuffer: Buffer used to transmit data in the ISR
* TXByteCtr: Number of bytes left to transfer
* TransmitIndex: The index of the next byte to be transmitted in TransmitBuffer
* */
uint8_t ReceiveBuffer[MAX_BUFFER_SIZE] = {0};
uint8_t RXByteCtr = 0;
uint8_t ReceiveIndex = 0;
uint8_t TransmitBuffer[MAX_BUFFER_SIZE] = {0};
uint8_t TXByteCtr = 0;
uint8_t TransmitIndex = 0;
/* I2C Write and Read Functions */
I2C_Mode I2C_Master_ReadDataBlocking(uint8_t dev_addr, uint8_t count);
void CopyArray_wCRC(uint8_t *source, uint8_t *dest, uint8_t count, uint16_t *CRC);
I2C_Mode I2C_Master_WriteCmdBlocking(uint8_t dev_addr, uint8_t cmd, uint8_t *payload, uint8_t count);
I2C_Mode I2C_Master_ReadDataBlocking(uint8_t dev_addr, uint8_t count)
{
if (count > MAX_BUFFER_SIZE)
{
return ERROR_MODE;
}
/* Initialize state machine */
RXByteCtr = count;
TXByteCtr = 0;
ReceiveIndex = 0;
TransmitIndex = 0;
/* Initialize slave address and interrupts */
UCB0I2CSA = dev_addr;
UCB0IFG &= ~(UCTXIFG + UCRXIFG); // Clear any pending interrupts
UCB0IE |= UCRXIE; // Enable RX interrupt
UCB0IE &= ~UCTXIE; // Disable TX interrupt
__disable_interrupt();
MasterMode = RX_DATA_MODE;
UCB0CTL1 &= ~UCTR;
UCB0CTL1 |= UCTXSTT; // I2C RX, start condition
while (MasterMode == RX_DATA_MODE)
{
__bis_SR_register(LPM0_bits + GIE); // Enter LPM0 w/ interrupts
__disable_interrupt();
}
return MasterMode;
}
I2C_Mode I2C_Master_Write_cmd(uint8_t dev_addr,uint8_t command)
{
uint16_t total_count=10;
uint8_t CRC_Calc = command+4;
// If size is OK, fill buffer
TransmitBuffer[0] = 0x55; // header
TransmitBuffer[1] = 0xAA; // header
TransmitBuffer[2] = 0x07; // packet length (ID, CMD, payload, checksum)
TransmitBuffer[3] = 0x04; // Design Center ID
TransmitBuffer[4] = command; // command
TransmitBuffer[5] = 0x00; //
TransmitBuffer[6] = 0x00; //
TransmitBuffer[7] = 0x00; //
TransmitBuffer[8] = CRC_Calc; // CRC
TransmitBuffer[9] = 0x00; // CRC
putsHexPC(TransmitBuffer,total_count);
TXByteCtr = total_count;
RXByteCtr = 0;
ReceiveIndex = 0;
TransmitIndex = 0;
/* Initialize slave address and interrupts */
UCB0I2CSA = dev_addr;
UCB0IFG &= ~(UCTXIFG + UCRXIFG); // Clear any pending interrupts
UCB0IE &= ~UCRXIE; // Disable RX interrupt
UCB0IE |= UCTXIE; // Enable TX interrupt
__disable_interrupt();
/* Initialize state machine */
MasterMode = TX_DATA_MODE;
UCB0CTL1 |= UCTR | UCTXSTT; // I2C RX, start condition
while(MasterMode == TX_DATA_MODE)
{
__bis_SR_register(LPM0_bits + GIE); // Enter LPM0 w/ interrupts
__disable_interrupt();
}
return MasterMode;
}
I2C_Mode I2C_Master_Write_Config(uint8_t dev_addr)
{
uint16_t total_count=9;
// If size is OK, fill buffer
TransmitBuffer[0] = 0x55; // header
TransmitBuffer[1] = 0xAA; // header
TransmitBuffer[2] = 0x06; // packet length (ID, CMD, payload, checksum)
TransmitBuffer[3] = 0x04; // Design Center ID
TransmitBuffer[4] = 0x01; // command
TransmitBuffer[5] = 0x01; // Write
TransmitBuffer[6] = 0x01; // Active
TransmitBuffer[7] = 0x07; // CRC
TransmitBuffer[8] = 0x00; // CRC
putsHexPC(TransmitBuffer,total_count);
TXByteCtr = total_count;
RXByteCtr = 0;
ReceiveIndex = 0;
TransmitIndex = 0;
/* Initialize slave address and interrupts */
UCB0I2CSA = dev_addr;
UCB0IFG &= ~(UCTXIFG + UCRXIFG); // Clear any pending interrupts
UCB0IE &= ~UCRXIE; // Disable RX interrupt
UCB0IE |= UCTXIE; // Enable TX interrupt
__disable_interrupt();
/* Initialize state machine */
MasterMode = TX_DATA_MODE;
UCB0CTL1 |= UCTR | UCTXSTT; // I2C RX, start condition
while(MasterMode == TX_DATA_MODE)
{
__bis_SR_register(LPM0_bits + GIE); // Enter LPM0 w/ interrupts
__disable_interrupt();
}
return MasterMode;
}
I2C_Mode I2C_Master_WriteCmdBlocking(uint8_t dev_addr, uint8_t cmd, uint8_t *payload, uint8_t count)
{
uint16_t total_count;
uint16_t CRC_Calc = 0x00;
//Total count is header (2 bytes) + length (1 byte) + DC ID (1 Byte) + CMD (1 byte) + payload (count) + checksum (2 bytes)
total_count = 7 + count;
if (total_count > MAX_BUFFER_SIZE)
{
return ERROR_MODE;
}
// If size is OK, fill buffer
TransmitBuffer[0] = 0x55; // header
TransmitBuffer[1] = 0xAA; // header
TransmitBuffer[2] = count+4; // packet length (ID, CMD, payload, checksum)
TransmitBuffer[3] = 0x04; // Design Center ID
TransmitBuffer[4] = cmd; // command
CRC_Calc = TransmitBuffer[3] + TransmitBuffer[4];
//Copy register data to TransmitBuffer
CopyArray_wCRC(payload, &TransmitBuffer[5], count, &CRC_Calc);
putsHexPC(TransmitBuffer,total_count);
TXByteCtr = total_count;
RXByteCtr = 0;
ReceiveIndex = 0;
TransmitIndex = 0;
/* Initialize slave address and interrupts */
UCB0I2CSA = dev_addr;
UCB0IFG &= ~(UCTXIFG + UCRXIFG); // Clear any pending interrupts
UCB0IE &= ~UCRXIE; // Disable RX interrupt
UCB0IE |= UCTXIE; // Enable TX interrupt
__disable_interrupt();
/* Initialize state machine */
MasterMode = TX_DATA_MODE;
UCB0CTL1 |= UCTR | UCTXSTT; // I2C RX, start condition
while(MasterMode == TX_DATA_MODE)
{
__bis_SR_register(LPM0_bits + GIE); // Enter LPM0 w/ interrupts
__disable_interrupt();
}
return MasterMode;
}
void CopyArray_wCRC(uint8_t *source, uint8_t *dest, uint8_t count, uint16_t *CRC)
{
uint8_t copyIndex = 0;
for (copyIndex = 0; copyIndex < count; copyIndex++)
{
dest[copyIndex] = source[copyIndex];
*CRC += source[copyIndex];
}
dest[copyIndex++] = (*CRC & 0xFF); // Store LSB CRC
dest[copyIndex] = (*CRC >> 8); // Store MSB CRC
}
//******************************************************************************
// Device Initialization *******************************************************
//******************************************************************************
void initClockTo16MHz()
{
UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO
UCSCTL4 |= SELA_2; // Set ACLK = REFO
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5; // Select DCO range 16MHz operation
UCSCTL2 = FLLD_0 + 487; // Set DCO Multiplier for 16MHz
// (N + 1) * FLLRef = Fdco
// (487 + 1) * 32768 = 16MHz
// Set FLL Div = fDCOCLK
__bic_SR_register(SCG0); // Enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 16 MHz / 32,768 Hz = 500000 = MCLK cycles for DCO to settle
__delay_cycles(500000);//
// Loop until XT1,XT2 & DCO fault flag is cleared
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
}
uint16_t setVCoreUp(uint8_t level){
uint32_t PMMRIE_backup, SVSMHCTL_backup, SVSMLCTL_backup;
//The code flow for increasing the Vcore has been altered to work around
//the erratum FLASH37.
//Please refer to the Errata sheet to know if a specific device is affected
//DO NOT ALTER THIS FUNCTION
//Open PMM registers for write access
PMMCTL0_H = 0xA5;
//Disable dedicated Interrupts
//Backup all registers
PMMRIE_backup = PMMRIE;
PMMRIE &= ~(SVMHVLRPE | SVSHPE | SVMLVLRPE |
SVSLPE | SVMHVLRIE | SVMHIE |
SVSMHDLYIE | SVMLVLRIE | SVMLIE |
SVSMLDLYIE
);
SVSMHCTL_backup = SVSMHCTL;
SVSMLCTL_backup = SVSMLCTL;
//Clear flags
PMMIFG = 0;
//Set SVM highside to new level and check if a VCore increase is possible
SVSMHCTL = SVMHE | SVSHE | (SVSMHRRL0 * level);
//Wait until SVM highside is settled
while((PMMIFG & SVSMHDLYIFG) == 0)
{
;
}
//Clear flag
PMMIFG &= ~SVSMHDLYIFG;
//Check if a VCore increase is possible
if((PMMIFG & SVMHIFG) == SVMHIFG)
{
//-> Vcc is too low for a Vcore increase
//recover the previous settings
PMMIFG &= ~SVSMHDLYIFG;
SVSMHCTL = SVSMHCTL_backup;
//Wait until SVM highside is settled
while((PMMIFG & SVSMHDLYIFG) == 0)
{
;
}
//Clear all Flags
PMMIFG &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG |
SVMLVLRIFG | SVMLIFG |
SVSMLDLYIFG
);
//Restore PMM interrupt enable register
PMMRIE = PMMRIE_backup;
//Lock PMM registers for write access
PMMCTL0_H = 0x00;
//return: voltage not set
return false;
}
//Set also SVS highside to new level
//Vcc is high enough for a Vcore increase
SVSMHCTL |= (SVSHRVL0 * level);
//Wait until SVM highside is settled
while((PMMIFG & SVSMHDLYIFG) == 0)
{
;
}
//Clear flag
PMMIFG &= ~SVSMHDLYIFG;
//Set VCore to new level
PMMCTL0_L = PMMCOREV0 * level;
//Set SVM, SVS low side to new level
SVSMLCTL = SVMLE | (SVSMLRRL0 * level) |
SVSLE | (SVSLRVL0 * level);
//Wait until SVM, SVS low side is settled
while((PMMIFG & SVSMLDLYIFG) == 0)
{
;
}
//Clear flag
PMMIFG &= ~SVSMLDLYIFG;
//SVS, SVM core and high side are now set to protect for the new core level
//Restore Low side settings
//Clear all other bits _except_ level settings
SVSMLCTL &= (SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 +
SVSMLRRL1 + SVSMLRRL2
);
//Clear level settings in the backup register,keep all other bits
SVSMLCTL_backup &=
~(SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 + SVSMLRRL1 + SVSMLRRL2);
//Restore low-side SVS monitor settings
SVSMLCTL |= SVSMLCTL_backup;
//Restore High side settings
//Clear all other bits except level settings
SVSMHCTL &= (SVSHRVL0 + SVSHRVL1 +
SVSMHRRL0 + SVSMHRRL1 +
SVSMHRRL2
);
//Clear level settings in the backup register,keep all other bits
SVSMHCTL_backup &=
~(SVSHRVL0 + SVSHRVL1 + SVSMHRRL0 + SVSMHRRL1 + SVSMHRRL2);
//Restore backup
SVSMHCTL |= SVSMHCTL_backup;
//Wait until high side, low side settled
while(((PMMIFG & SVSMLDLYIFG) == 0) &&
((PMMIFG & SVSMHDLYIFG) == 0))
{
;
}
//Clear all Flags
PMMIFG &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG |
SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG
);
//Restore PMM interrupt enable register
PMMRIE = PMMRIE_backup;
//Lock PMM registers for write access
PMMCTL0_H = 0x00;
return true;
}
bool increaseVCoreToLevel2()
{
uint8_t level = 2;
uint8_t actlevel;
bool status = true;
//Set Mask for Max. level
level &= PMMCOREV_3;
//Get actual VCore
actlevel = PMMCTL0 & PMMCOREV_3;
//step by step increase or decrease
while((level != actlevel) && (status == true))
{
if(level > actlevel)
{
status = setVCoreUp(++actlevel);
}
else
{
status = false;
}
}
return (status);
}
void initGPIO()
{
//LEDs
P1OUT = 0x00; // P1 setup for LED & reset output
P1DIR |= BIT0;
P4DIR |= BIT7;
P4OUT &= ~(BIT7);
//I2C Pins
P3SEL |= BIT0 + BIT1 + BIT3 + BIT4; // P3.0,1 option select
// P3.4,5 = USCI_A0 TXD/RXD
}
void initGPIO_UART()
{
// P3SEL = BIT3 + BIT4; // P3.4,5 = USCI_A0 TXD/RXD
// P5SEL |= BIT4+BIT5; // Select XT1
}
void initI2C()
{
UCB0CTL1 |= UCSWRST; // Enable SW reset
UCB0CTL0 = UCMST + UCMODE_3 + UCSYNC; // I2C Master, synchronous mode
UCB0CTL1 = UCSSEL_2 + UCSWRST; // Use SMCLK, keep SW reset
UCB0BR0 = 160; // fSCL = SMCLK/160 = ~100kHz
UCB0BR1 = 0;
UCB0I2CSA = SLAVE_ADDR; // Slave Address is 048h
UCB0CTL1 &= ~UCSWRST; // Clear SW reset, resume operation
UCB0IE |= UCNACKIE;
}
//******************************************************************************
// Main ************************************************************************
// Send and receive three messages containing the example commands *************
//******************************************************************************
int main(void) {
uint8_t i,cnt;
WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer
increaseVCoreToLevel2();
initClockTo16MHz();
initGPIO();initGPIO_UART();
initI2C();
initUART();
putsUART("Hello ");
putsUART("\nConfig: ");
// __bis_SR_register(LPM0_bits + GIE); // Since SMCLK is source, enter LPM0, interrupts enabled
// I2C_Master_WriteCmdBlocking(SLAVE_ADDR, CMD_01_MASTER, MasterCMD01Payload, CMD_01_LENGTH);
I2C_Master_Write_Config(SLAVE_ADDR);
while (1)
{
cnt++;
if(cnt>4)cnt=0;
putsUART("\nCmd Read: ");
I2C_Master_Write_cmd(SLAVE_ADDR,0x80+cnt);
__delay_cycles(1000000);
I2C_Master_ReadDataBlocking(SLAVE_ADDR, RESPONSE_SLAVE_LENGTH);
putsUART("\nData Read: ");
for(i=0;i<15;i++) {
putHexUART(ReceiveBuffer[i]);
putcUART(' ');
}
// Check response in Receive buffer
}
}
//******************************************************************************
// I2C Interrupt ***************************************************************
//******************************************************************************
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=USCI_B0_VECTOR
__interrupt void USCI_B0_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(USCI_B0_VECTOR))) USCI_B0_ISR (void)
#else
#error Compiler not supported!
#endif
{
//Must read from UCB0RXBUF
uint8_t rx_val = 0;
switch(__even_in_range(UCB0IV,0xC))
{
case USCI_NONE:break; // Vector 0 - no interrupt
case USCI_I2C_UCALIFG:break; // Interrupt Vector: I2C Mode: UCALIFG
case USCI_I2C_UCNACKIFG:break; // Interrupt Vector: I2C Mode: UCNACKIFG
case USCI_I2C_UCSTTIFG:break; // Interrupt Vector: I2C Mode: UCSTTIFG
case USCI_I2C_UCSTPIFG:break; // Interrupt Vector: I2C Mode: UCSTPIFG
case USCI_I2C_UCRXIFG:
rx_val = UCB0RXBUF;
if (RXByteCtr)
{
ReceiveBuffer[ReceiveIndex++] = rx_val;
RXByteCtr--;
}
if (RXByteCtr == 1)
{
UCB0CTL1 |= UCTXSTP;
}
else if (RXByteCtr == 0)
{
UCB0IE &= ~UCRXIE;
MasterMode = IDLE_MODE;
update=1;
__bic_SR_register_on_exit(CPUOFF); // Exit LPM0
}
break; // Interrupt Vector: I2C Mode: UCRXIFG
case USCI_I2C_UCTXIFG:
if (TXByteCtr)
{
UCB0TXBUF = TransmitBuffer[TransmitIndex++];
TXByteCtr--;
}
else
{
//Done with transmission
UCB0CTL1 |= UCTXSTP; // Send stop condition
MasterMode = IDLE_MODE;
UCB0IE &= ~UCTXIE; // disable TX interrupt
__bic_SR_register_on_exit(CPUOFF); // Exit LPM0
}
break; // Interrupt Vector: I2C Mode: UCTXIFG
default: break;
}
}
//******************************************************************************
// UART RX Interrupt ***********************************************************
//******************************************************************************
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=USCI_A0_VECTOR
__interrupt void USCI_A0_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(USCI_A0_VECTOR))) USCI_A0_ISR (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(UCA0IV,4))
{
case 0:break; // Vector 0 - no interrupt
case 2: // Vector 2 - RXIFG
while (!(UCA0IFG & UCTXIFG)); // USCI_A0 TX buffer ready?
UCA0TXBUF = UCA0RXBUF; // TX -> RXed character
break;
case 4:break; // Vector 4 - TXIFG
default: break;
}
}
数据读取结果。
