[参考译文] MSP430F5438A：使用 VCC 参考时、ADC 手动转换挂起

我们能够确认问题出在 MCU 而不是电路板。  我还创建了一个示例程序(基于 TI 自己的"msp430x54xA_ADC12_09.c"示例程序)、该程序与我们发现的问题相同。

以下程序在未对 正常工作的 MCU 进行修改的情况下运行。 在一个有故障的 MCU 上、第一个 ADC 转换请求将会成功、但第二个请求将导致 程序挂起。 所请求的转换从不会发生、因此 ICR 从不会被触发。

有3种"权变措施"被注释掉。 取消注释这三种权变措施中的任何一种都会允许程序在有故障的 MCU 上运行、但 我认为 如果 MCU 符合规范(SLAU208Q)、这两种权变措施都不是必需的。

我不 排除 编程有误或者  安装了 MCU 的电路板有问题的可能性、我欢迎 对 我的发现提出质疑的任何讨论。

否则、我希望这会对其他可能遇到同样问题的人有所帮助。  

#include <msp430.h>

volatile unsigned int results[13];

int main(void)
{
  WDTCTL = WDTPW+WDTHOLD;                   // Stop watchdog timer

  // Enable A/D channel inputs
  P6SEL = 0xE0;
  P7SEL = 0x30;

  // Enable VREF=2.5V shared reference, disable temperature sensor
  REFCTL0 |= REFMSTR+REFVSEL_2+REFON+REFTCOFF;

  ADC12CTL0 = ADC12ON+ADC12MSC+ADC12SHT0_2; // Turn on ADC12, set sampling time
  ADC12CTL1 = ADC12SHP+ADC12CONSEQ_1;       // Use sampling timer, single sequence
  ADC12MCTL0 = ADC12INCH_5+ADC12SREF_1;     // Ref=VREF, channel = A5
  ADC12MCTL1 = ADC12INCH_5+ADC12SREF_1;
  ADC12MCTL2 = ADC12INCH_5+ADC12SREF_1;
  ADC12MCTL3 = ADC12INCH_6+ADC12SREF_1;     // Ref=VREF, channel = A6
  ADC12MCTL4 = ADC12INCH_6+ADC12SREF_1;
  ADC12MCTL5 = ADC12INCH_6+ADC12SREF_1;
  ADC12MCTL6 = ADC12INCH_7+ADC12SREF_1;     // Ref=VREF, channel = A7
  ADC12MCTL7 = ADC12INCH_7+ADC12SREF_1;
  ADC12MCTL8 = ADC12INCH_7+ADC12SREF_1;
  ADC12MCTL9 = ADC12INCH_12;                // Ref=Vcc, channel = A12
  ADC12MCTL10 = ADC12INCH_12;
  ADC12MCTL11 = ADC12INCH_12;
  ADC12MCTL12 = ADC12INCH_13 + ADC12EOS;    // Ref=Vcc, channel = A13
  ADC12IE = 0x08;                           // Enable ADC12IFG.3
  ADC12CTL0 |= ADC12ENC;                    // Enable conversions

  while(1)
  {
    ADC12CTL0 |= ADC12SC;                   // Start convn - software trigger

    // Workaround 1 - Set conversion bit twice
    /*
    ADC12CTL0 |= ADC12SC;
    */

    // Workaround 2 - Reset enable bit between conversions
    /*
    ADC12CTL0 &=~ADC12SC;
    ADC12CTL0 &=~ADC12ENC;
    ADC12CTL0 |= ADC12SC + ADC12ENC;
    */

    __bis_SR_register(LPM4_bits + GIE);     // Enter LPM4, Enable interrupts
    __no_operation();                       // For debugger
  }
}

#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=ADC12_VECTOR
__interrupt void ADC12ISR (void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(ADC12_VECTOR))) ADC12ISR (void)
#else
#error Compiler not supported!
#endif
{
  switch(__even_in_range(ADC12IV,34))
  {
  case  0: break;                           // Vector  0:  No interrupt
  case  2: break;                           // Vector  2:  ADC overflow
  case  4: break;                           // Vector  4:  ADC timing overflow
  case  6: break;                           // Vector  6:  ADC12IFG0
  case  8: break;                           // Vector  8:  ADC12IFG1
  case 10: break;                           // Vector 10:  ADC12IFG2
  case 12:                                  // Vector 12:  ADC12IFG3
    ADC12CTL0 &=~ADC12SC;                   // For sequence-of-Channels mode, ADC12SC must be cleared by software after each sequence to trigger another sequence
    results[0] = ADC12MEM0;                 // Move results, IFG is cleared
    results[1] = ADC12MEM1;                 // Move results, IFG is cleared
    results[2] = ADC12MEM2;                 // Move results, IFG is cleared
    results[3] = ADC12MEM3;                 // Move results, IFG is cleared
    results[4] = ADC12MEM4;                 // Move results, IFG is cleared
    results[5] = ADC12MEM5;                 // Move results, IFG is cleared
    results[6] = ADC12MEM6;                 // Move results, IFG is cleared
    results[7] = ADC12MEM7;                 // Move results, IFG is cleared
    results[8] = ADC12MEM8;                 // Move results, IFG is cleared
    results[9] = ADC12MEM9;                 // Move results, IFG is cleared
    results[10] = ADC12MEM10;               // Move results, IFG is cleared
    results[11] = ADC12MEM11;               // Move results, IFG is cleared
    results[12] = ADC12MEM12;               // Move results, IFG is cleared

    // Workaround 3 - Reset conversion bit after reading memory
    /*
    ADC12CTL0 &=~ADC12SC;
    */

    __bic_SR_register_on_exit(LPM4_bits);   // Exit active CPU, SET BREAKPOINT HERE
  case 14: break;                           // Vector 14:  ADC12IFG4
  case 16: break;                           // Vector 16:  ADC12IFG5
  case 18: break;                           // Vector 18:  ADC12IFG6
  case 20: break;                           // Vector 20:  ADC12IFG7
  case 22: break;                           // Vector 22:  ADC12IFG8
  case 24: break;                           // Vector 24:  ADC12IFG9
  case 26: break;                           // Vector 26:  ADC12IFG10
  case 28: break;                           // Vector 28:  ADC12IFG11
  case 30: break;                           // Vector 30:  ADC12IFG12
  case 32: break;                           // Vector 32:  ADC12IFG13
  case 34: break;                           // Vector 34:  ADC12IFG14
  default: break;
  }
}