[参考译文] TMS320C6711D：TMS32C6711DGDPA167的 PLL 配置中可能缺少哪些内容以导致频繁启动故障？

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1069011/tms320c6711d-what-could-be-missing-in-pll-configuration-of-tms32c6711dgdpa167-to-cause-frequent-starting-up-failures

无效 PLL_Configuration()

              ｛

              内部 I；      //JFV 2006年30月11日 ，此处用于等待循环

              //PLLCSR &= 0xFFFFFFFE；                           //将 PLLEN 设置为0

              PLLCSR = 0x40；                                             //将 PLLEN 设置为0

              对于(i=0；i<5；i++)

                             ｛｝                                                                                     //等待4个 CLKIN 循环

              //PLLCSR |= 0x00000008；                          //将 PLLRST 设置为1

              PLLCSR = 0x48；                                             //将 PLLRST 设置为1

              //Registre PLLDIV0，部门标准值9 => PLLREF

              PLLDIV0 = 0x0008008；                 // 60MHz/9=6.66Mhz

              //Registre PLLM，乘数为18 => PLLUT

              PLLM = 0x00000012；                                   // 6.66MHz*18=120MHz

              //Registre OSCDIV1,部门参数1 => CLKOUT3

              OSCDIV1 = 0x00008002；                             //Division PAR 3 (60MHz/3 = 20 MHz)

              //Registre PLLDIV1，部门参数1 => SYSCLK1.

              PLLDIV1 = 0x00008000；               // 120MHz/1 = 120MHz

              对于(i=0；i<9；i++)

                             ｛｝                                                                                     //等待8个 CLKIN 循环

              //Registre PLLDIV2，部门参数2 => SYSCLK2.

              PLLDIV2 = 0x00008001；               // 120MHz/2=60MHz

              对于(i=0；i<9；i++)

                             ｛｝                                                                                     //等待8个 CLKIN 循环

              //Registre PLLDIV3，部门参数2 => SYSCLK3

              PLLDIV3 = 0x00008001；               // 120MHz/2=60MHz

              对于(i=0；i<9；i++)

                             {}//                                                                                     等待 PLL 重置(125ns)

              //PLLCSR &= 0xFFF7；                                   //将 PLLRST 设置为0

              PLLCSR = 0x40；                                             //将 PLLRST 设置为0

              对于(i=0；i<11280; i++)

                             ｛｝                                                                                     //等待 PLL 锁定最大188us

              //PLLCSR |= 0x00000001；           //将 PLLEN 设置为1

              PLLCSR = 0x01；                              //将 PLLEN 设置为1

              }