主题中讨论的其他器件: TLV320AIC3254、 TDA4VM
大家好!
在 TDA4VE-Q1上设置 MCASP 时出现问题。
我们要将 MCASP 配置为与 TLV320AIC3254编解码器进行 I2S 通信的主器件。
其理念是 McASP0提供 MCLK、BCLK 和 WCLK。 现在、我们可以在 ACLKX 和 AFSX 上看到 BCLK 和 WCLK、频率刚好处于开启状态、它 随我们选择的采样率而变化、因此 我们假定 MCASP 配置正确。
不过、MCLK 信号存在问题。 它接缝我们无法将 MCLK (AHCLKX)配置为多路复用至 AUDIO_EXT_REFCLK1引脚。
对于初学者、我们尝试在 AUDIO_EXT_REFCLK1上设置固定时钟速率、但在 Y25焊盘上无法获得任何内容。
我们按照 k3-j721e-common-proc-board.dts 文件来说明如何配置、因为该电路板具有类似的 MCASP->codec 设置。
以下是我们已有的 DTS 片段:
/ { mcasp0: mcasp@2b00000 { compatible = "ti,am33xx-mcasp-audio"; #sound-dai-cells = <0>; reg = <0x0 0x02b00000 0x0 0x2000>, <0x0 0x02b08000 0x0 0x400>; reg-names = "mpu","dat"; pinctrl-names = "default"; pinctrl-0 = <&mcasp0_pins>; op-mode = <0>; /* MCASP_IIS_MODE */ tdm-slots = <2>; /* 4 serializers */ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 >; interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; /* MCASP0_XMIT_INTR_PEND_0, MCASP0_REC_INTR_PEND_0 */ interrupt-names = "tx", "rx"; tx-num-evt = <32>; rx-num-evt = <32>; dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; /* navss_main_pdma_main_mcasp_tx0, navss_main_pdma_main_mcasp_rx0 */ dma-names = "tx", "rx"; /* DEV_MCASP0_AUX_CLK */ clocks = <&k3_clks 209 0>; clock-names = "fck"; /* HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK -> DEV_MCASP0_AUX_CLK */ assigned-clocks = <&k3_clks 209 0>; assigned-clock-parents = <&k3_clks 209 1>; assigned-clock-rates = <24576000>; power-domains = <&k3_pds 209 TI_SCI_PD_EXCLUSIVE>; }; sound { compatible = "simple-audio-card"; simple-audio-card,name = "TLV320AIC3254"; simple-audio-card,widgets = "Headphone", "Headphone Jack"; simple-audio-card,format = "i2s"; simple-audio-card,bitclock-master = <&link0_cpu>; simple-audio-card,frame-master = <&link0_cpu>; simple-audio-card,bitclock-inversion; link0_cpu: simple-audio-card,cpu { sound-dai = <&mcasp0>; system-clock-direction-out; system-clock-frequency = <24576000>; }; link0_codec: simple-audio-card,codec { sound-dai = <&tlv320aic32x4>; }; }; }; &k3_clks { /* Confiure AUDIO_EXT_REFCLK1 pin as output */ pinctrl-names = "default"; pinctrl-0 = <&audio_ext_refclk1_pins_default>; }; &main_i2c2 { tlv320aic32x4: audio-codec@18 { compatible = "ti,tlv320aic32x4"; reg = <0x18>; #sound-dai-cells= <0>; /* AUDIO_EXT_REFCLK_1 -> MCAN2_RX (Y25)*/ clocks = <&k3_clks 157 299>; clock-names = "mclk"; // /* MCASP_MAIN_0_MCASP_AHCLKX_POUT -> REFCLK1 */ assigned-clocks = <&k3_clks 157 299>; assigned-clock-parents = <&k3_clks 157 328>; assigned-clock-rates = <24576000>; /* for 48KHz */ ldoin-supply = <®_audio_3v3>; iov-supply = <®_audio_3v3>; }; }; &main_pmx0 { audio_ext_refclk1_pins_default: audio-ext-refclk1-pins-default { pinctrl-single,pins = < J721S2_IOPAD(0x078, PIN_OUTPUT, 1) /* (Y25) MCAN2_RX.AUDIO_EXT_REFCLK1 */ >; }; mcasp0_pins: mcasp0-pins-deafult { pinctrl-single,pins = < J721S2_IOPAD(0x03C, PIN_OUTPUT, 1) /* (U27) WCLK, MCASP0_AFSX.MCASP0_AFSX */ J721S2_IOPAD(0x038, PIN_OUTPUT, 1) /* (AB28) BCLK, MCASP0_ACLKX.MCASP0_ACLKX */ J721S2_IOPAD(0x040, PIN_INPUT_PULLDOWN, 1) /* (AC28) DOUT, MCASP0_AXR0.MCASP0_AXR0 */ J721S2_IOPAD(0x07C, PIN_OUTPUT_PULLDOWN, 1) /* (T27) DIN, MCASP0_AXR3.MCASP0_AXR3 */ >; }; };
因此、我们假设 Y25引脚上应该存在 MCLK 时钟:
HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK (24.576.000Hz)-> AUDIO_EXT_REFCLK1 -> Y25
k3conf 正在显示:
$ k3conf dump clocks 157 ... | 157 | 299 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN | CLK_STATE_READY | 24576000 | | 157 | 300 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 301 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 302 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 303 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 304 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 312 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 313 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 314 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 315 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 316 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 324 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 157 | 325 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 157 | 326 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 157 | 327 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 157 | 328 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 24576000 |
有什么缺失吗? 也许某些 pinctrl 设置或时钟设置应该到位?
非常感谢您提供任何帮助。
P.S。我们还检查了连接探头的输出引脚与 Y25焊盘之间是否存在一些硬件问题、所有连接正常(如果标记了 AUDIO_EXT_REFCLK 引脚、我们可以看到该引脚被拉至高/低电平、 如果我们将焊盘配置为 GPIO0_30、我们可以驱动它并查看示波器上的变化)。