[参考译文] AM6548：icssg_prueth 不在 MII 模式下传输

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Other Parts Discussed in Thread: AM6548, TMDX654IDKEVM

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1209213/am6548-icssg_prueth-does-not-transmit-in-mii-mode

器件型号：AM6548
主题中讨论的其他器件： TMDX654IDKEVM

我们的硬件设计使用3个 ICSSG、如下所示：

一个采用双 EMAC 模式、连接2个 MII 的 DP83822 10/100Mbps PHY
一个在单 EMAC 模式下、并通过一个 RGMII_ID 连接 DP83867 1Gps PHY
一个采用单 EMAC 模式、具有固定100Mbps FD MII 接口

处于 RGMII_ID 模式的 PRU 正常工作。 MII 模式下的三个 PRU 似乎能够接收数据(我们在 ARP 缓存中看到一个对等 MAC 地址)、但无法传输。

我们认为硬件设计是正确的(TX 线路交换到相反的 PRU 切片、如 MII 模式的相关文档所述)。

MDIO 配置正确、检测到链路建立/断开事件、并且速度/双工显示正确。在内核中启用 k3_ringacc 动态调试事件会显示每个已传输数据包的 ringacc 推送和弹出活动。 PHY 已正确复位、TX 和 RX 时钟以预期的速率(25MHz 或2.5MHz、根据速度)进行节拍。但在 MII 总线上、TXEN 信号是恒定的零。

我们使用最新的系统和 PRU 固件、ti-linux-kernel 08.06.00.007 (commit 2c23e6c538c879e380401ae4b236f54020618eaa)以及随附的 DTS 和内核配置文件。

我们的感觉是,在 MII 模式下,最新的 PRU 固件可能会有问题,因为在以太网驱动程序和 ringacc 级别,一切似乎都可以,但在 MII TX 端没有发生。是否有任何证据表明最新 PRU 固件在 MII 模式下成功传输？如果可以，请将相应的 DTS 文件发送给我们进行比较。

谢谢、此致、

丹尼尔·马米尔

1 年多前

0 admin 1 年多前

TI__Guru**** 657500 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

您好！

您能解释几个要点吗？您在使用哪种 AM6548器件版本？相同的硬件和 MII 接口是否适用于某个早期软件版本？

佩卡

0 admin 1 年多前

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尊敬的 Pekka：

我们使用的是 SR 2.0

我不记得它是否适用于早期的软件版本。我们可能一开始就只有千兆运行。

丹尼尔

0 admin 1 年多前

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我们相信硬件设计是正确的(按照 MII 模式的说明、TX 线路被交换到相反的 PRU 切片)。

您能否针对 MII 指出此指南？

0 admin 1 年多前

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来自 TRM：

"6.5.11.2.6.3 PRU 和 MII 端口多路复用器

MII_G_RT 模块支持可配置的 PRU 内核到 MII TXN/RXn 端口的映射。默认情况下、PRU0映射到 TX1和 RX0、PRU1映射到 TX0和 RX1。但是、系统支持灵活地将任何 PRU 内核映射到任何 TX 和 RX 端口。例如、PRU0的输入可以是 RX_MII0或 RX_MII1。同样、TX_MII0的输入可以是 PRU0或 PRU1。"

另外从表6-1672 (ICSSG_TXCFG0[TX_MUX_SEL0]的说明)中也可以看到：

" TX 端口0的默认/复位设置为1。此设置允许 MII TX 端口0从 PRU1以及默认连接到 PRU1的 MII RX 端口1接收数据。

对于 MII TX 端口1、默认为零、这允许它从默认连接到 PRU0的 PRU0和 MII0接收数据。"

0 admin 1 年多前

TI__Guru**** 657500 points

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我仍然不确定应该交换的原因、TRM 部分确实说可以交换、但我在软件文档中找不到需要交换的任何内容。 ICSSG MII 的 DTS 文件位于/board-support/ /arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac-mii.dts。这是在具有相同 ICSSG 的较新 AM64x 器件上。

您是否可以共享您拥有的 DTS 文件、您提到了在上面附加它、但我没有看到它附有。

佩卡

0 admin 1 年多前

TI__Guru**** 657500 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

尊敬的 Pekka：

Linux 驱动程序在 MII 模式下无条件交换(可能是由于某些芯片的限制); 查看函数 icssg_config_mii_init 在 iccsg_config.c 中,以下是该代码的注释:"在 MII 模式下 TX 线在 ICSSG 内交换,所以 TX_MUX_cfg SEL 也需要交换与 RGMII 模式比较。 TODO：错误？"。

很抱歉 DTS 缺失、这里是、由于某种原因、我无法将其作为文件加入：

/*
 * Copyright (C) 2022 HaslerRail AG, Freiburgstrasse 251, CH-3018 Bern
 *
 * Daniel Marmier <daniel.marmier@haslerrail.com>
 */

/dts-v1/;

#include "../ti/k3-am654.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/phy/phy-am654-serdes.h>

/ {
	compatible =  "ti,am654-evm", "ti,am654";
	model = "HaslerRail AM65x TELOC";

/*
	aliases {
		ethernet1 = &icssg2_emac0;
		ethernet2 = &icssg2_emac1;
	};
*/

	chosen {
		stdout-path = "serial2:115200n8";
		bootargs = "earlycon=ns16550a,mmio32,0x02800000";
	};

	memory@80000000 {
		device_type = "memory";
		/* 1 GiB RAM */
		reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		secure_ddr: secure-ddr@9e800000 {
			reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
			alignment = <0x1000>;
			no-map;
		};
	};

	vcc3v3_io: fixedregulator-vcc3v3io {
		compatible = "regulator-fixed";
		regulator-name = "vcc3v3_io";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	/* Dual Ethernet application node on PRU-ICSSG0 */
	icssg0_eth: icssg0-eth {
		compatible = "ti,am654-icssg-prueth";
		pinctrl-names = "default";
		pinctrl-0 = <&icssg0_mii_pins_default>;
		sram = <&msmc_ram>;
		ti,prus = <&pru0_0 &rtu0_0 &tx_pru0_0>,
			  <&pru0_1 &rtu0_1 &tx_pru0_1>;
		ti,pruss-gp-mux-sel = <2 2 2>, <2 2 2>; /* both in MII mode */
		mii-g-rt = <&icssg0_mii_g_rt>;
		mii-rt = <&icssg0_mii_rt>;
		iep = <&icssg0_iep0 &icssg0_iep1>;
		interrupt-parent = <&icssg0_intc>;
		interrupts = <24 0 2>, <25 1 3>;
		interrupt-names = "tx_ts0", "tx_ts1";
		dmas = <&main_udmap 0xc100>, /* egress slice 0 */
		       <&main_udmap 0xc101>, /* egress slice 0 */
		       <&main_udmap 0xc102>, /* egress slice 0 */
		       <&main_udmap 0xc103>, /* egress slice 0 */
 		       <&main_udmap 0xc104>, /* egress slice 1 */
		       <&main_udmap 0xc105>, /* egress slice 1 */
		       <&main_udmap 0xc106>, /* egress slice 1 */
		       <&main_udmap 0xc107>, /* egress slice 1 */
		       <&main_udmap 0x4100>, /* ingress slice 0 */
		       <&main_udmap 0x4101>, /* ingress slice 1 */
               <&main_udmap 0x4102>, /* mgmnt rsp slice 0 */
               <&main_udmap 0x4103>; /* mgmnt rsp slice 1 */
 		dma-names =
			"tx0-0", "tx0-1", "tx0-2", "tx0-3",
			"tx1-0", "tx1-1", "tx1-2", "tx1-3",
			"rx0", "rx1", "rxmgm0", "rxmgm1";

		icssg0_emac0: ethernet-mii0 {
			phy-handle = <&icssg0_phy0>;
			phy-mode = "mii";
			syscon-rgmii-delay = <&scm_conf 0x4100>;
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};

		icssg0_emac1: ethernet-mii1 {
			phy-handle = <&icssg0_phy1>;
			phy-mode = "mii";
			syscon-rgmii-delay = <&scm_conf 0x4104>;
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};
	};

	/* Single Ethernet application node on PRU-ICSSG1 */
	icssg1_eth: icssg1-eth {
		compatible = "ti,am654-icssg-prueth";
		pinctrl-names = "default";
		pinctrl-0 = <&icssg1_rgmii_pins_default>;
		sram = <&msmc_ram>;
		ti,prus = <&pru1_0 &rtu1_0 &tx_pru1_0>;
		ti,pruss-gp-mux-sel = <2 2 2>, <2 2 2>; /* MII mode */
		mii-g-rt = <&icssg1_mii_g_rt>;
		mii-rt = <&icssg1_mii_rt>;
		iep = <&icssg1_iep0>, <&icssg1_iep1>;
		interrupt-parent = <&icssg1_intc>;
		interrupts = <24 0 2>, <25 1 3>;
		interrupt-names = "tx_ts0";
		dmas = <&main_udmap 0xc200>, /* egress slice 0 */
		       <&main_udmap 0xc201>, /* egress slice 0 */
		       <&main_udmap 0xc202>, /* egress slice 0 */
		       <&main_udmap 0xc203>, /* egress slice 0 */
		       <&main_udmap 0x4200>, /* ingress slice 0 */
               <&main_udmap 0x4202>; /* mgmnt rsp slice 0 */
		dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", "rx0", "rxmgm0";

		icssg1_emac0: ethernet-mii0 {
			phy-handle = <&icssg1_phy0>;
			phy-connection-type = "rgmii-id";
			syscon-rgmii-delay = <&scm_conf 0x4110>;
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};
	};

	/* Single Ethercat application node on PRU-ICSSG2 */
	icssg2_eth: icssg2-eth {
		compatible = "ti,am654-icssg-prueth";
		pinctrl-names = "default";
		pinctrl-0 = <&icssg2_mii_pins_default>;
		sram = <&msmc_ram>;
		ti,prus = <&pru2_0 &rtu2_0 &tx_pru2_0>,
			  <&pru2_1 &rtu2_1 &tx_pru2_1>;
		ti,pruss-gp-mux-sel = <2 2 2>, <2 2 2>; /* MII mode */
		mii-g-rt = <&icssg2_mii_g_rt>;
		mii-rt = <&icssg2_mii_rt>;
		iep = <&icssg2_iep0>, <&icssg2_iep1>;
		interrupt-parent = <&icssg2_intc>;
		interrupts = <24 0 2>;
		interrupt-names = "tx_ts0", "tx_ts1";
		dmas = <&main_udmap 0xc300>, /* egress slice 0 */
		       <&main_udmap 0xc301>, /* egress slice 0 */
		       <&main_udmap 0xc302>, /* egress slice 0 */
		       <&main_udmap 0xc303>, /* egress slice 0 */
		       <&main_udmap 0xc304>, /* egress slice 1 */
		       <&main_udmap 0xc305>, /* egress slice 1 */
		       <&main_udmap 0xc306>, /* egress slice 1 */
		       <&main_udmap 0xc307>, /* egress slice 1 */

		       <&main_udmap 0x4300>, /* ingress slice 0 */
		       <&main_udmap 0x4301>, /* ingress slice 1 */
		       <&main_udmap 0x4302>, /* mgmnt rsp slice 0 */
		       <&main_udmap 0x4303>; /* mgmnt rsp slice 1 */
		dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
			    "tx1-0", "tx1-1", "tx1-2", "tx1-3",
			    "rx0", "rx1",
			    "rxmgm0", "rxmgm1";

		icssg2_emac0: ethernet-mii0 {
			phy-mode = "mii";
			syscon-rgmii-delay = <&scm_conf 0x4120>;
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
			iep = <&icssg2_iep0>;
			fixed-link {
				speed = <100>;
				full-duplex;
			};
		};

		icssg2_emac1: ethernet-mii1 {
			phy-mode = "mii";
			syscon-rgmii-delay = <&scm_conf 0x4124>;
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
			fixed-link {
				speed = <100>;
				full-duplex;
			};
		};
	};
/*
	sdhci0_pwrseq: sdhci0-pwrseq {
		compatible = "mmc-pwrseq-emmc";
		reset-gpios = <&main_gpio0 7 GPIO_ACTIVE_LOW>;
	};
*/
/*
	sdhci0_pwrseq: sdhci0-pwrseq {
		compatible = "mmc-pwrseq-simple";
		reset-gpios = <&main_gpio0 7 GPIO_ACTIVE_LOW>;
		post-power-on-delay-ms = <5000>;
	};
*/
};

&wkup_pmx0 {
	wkup_i2c0_pins_default: wkup-i2c0-pins-default {
		pinctrl-single,pins = <
			AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT,  0)	/* (AC7) WKUP_I2C0_SCL */
			AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT,  0)	/* (AD6) WKUP_I2C0_SDA */
		>;
	};

	mcu_spi0_pins_default: mcu-spi0-pins-default {
		pinctrl-single,pins = <
			AM65X_WKUP_IOPAD(0x0090, PIN_OUTPUT, 0)	/*  (Y1) MCU_SPI0_CLK */
			AM65X_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0)	/*  (Y4) MCU_SPI0_CS0 */
			AM65X_WKUP_IOPAD(0x004c, PIN_OUTPUT, 5)	/*  (P1) MCU_SPI0_CS1 */
			AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 5)	/*  (N3) MCU_SPI0_CS2 */
			AM65X_WKUP_IOPAD(0x00c0, PIN_OUTPUT, 2)	/* (AC3) MCU_SPI0_CS3 */
			AM65X_WKUP_IOPAD(0x0094, PIN_OUTPUT, 0)	/*  (Y3) MCU_SPI0_D0 */
			AM65X_WKUP_IOPAD(0x0098, PIN_INPUT,  0)	/*  (Y2) MCU_SPI0_D1 */
		>;
	};

	wkup_gpio0_pins_default: wkup-gpio0-pins-default {
		pinctrl-single,pins = <
			AM65X_WKUP_IOPAD(0x00d8, PIN_OUTPUT, 7)	/* (AB3) WKUP_GPIO0_10 TP501 */
			AM65X_WKUP_IOPAD(0x00dc, PIN_OUTPUT, 7)	/* (AB2) WKUP_GPIO0_11 TP502 */
		>;
	};
};

&main_pmx0 {
	ecat_pins_default: ecat-pins-default {
		pinctrl-single,pins = <
			AM65X_IOPAD(0x0094, PIN_INPUT, 7) /*  (AC19) GPIO0_37 EEPROM_LOADED */
		>;
	};

	main_gpio0_pins_default: main-gpio0-pins-default {
		pinctrl-single,pins = <
			AM65X_IOPAD(0x000c, PIN_OUTPUT_PULLUP, 7) /*  (M24) GPIO0_3 LED_RSTn */
			AM65X_IOPAD(0x001c, PIN_OUTPUT, 7) /*  (M25) eMMC_RSTn */
			AM65X_IOPAD(0x002c, PIN_OUTPUT, 7) /*  (P27) GPIO0_11 USB_RSTn */
			AM65X_IOPAD(0x00ac, PIN_INPUT,  7) /* (AH15) GPIO0_43 PCA9539_INTn */
			AM65X_IOPAD(0x00b0, PIN_OUTPUT_PULLUP, 7) /* (AC16) GPIO0_44 I2C_RESETn */
		>;
	};

/*
	main_gpio1_pins_default: main-gpio1-pins-default {
		pinctrl-single,pins = <
			AM65X_IOPAD(0x0210, PIN_OUTPUT, 7) / * (U27) GPIO1_36 Eth1_RSTn * /
			AM65X_IOPAD(0x023c, PIN_OUTPUT, 7) / * (V25) GPIO1_47 Eth2_RSTn * /
			AM65X_IOPAD(0x0288, PIN_OUTPUT, 7) / * (Y27) GPIO1_66 Eth3_RSTn * /
		>;
	};
*/

	main_uart0_pins_default: main-uart0-pins-default {
		pinctrl-single,pins = <
			AM65X_IOPAD(0x01e4, PIN_INPUT,  0) /* (AF11) UART0_RXD */
			AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
		>;
	};

	main_i2c2_pins_default: main-i2c2-pins-default {
		pinctrl-single,pins = <
			AM65X_IOPAD(0x0074, PIN_INPUT,  5) /* (T27) GPMC0_CSn3.I2C2_SCL */
			AM65X_IOPAD(0x0070, PIN_INPUT,  5) /* (R25) GPMC0_CSn2.I2C2_SDA */
		>;
	};

	main_i2c3_pins_default: main-i2c3-pins-default {
		pinctrl-single,pins = <
			AM65X_IOPAD(0x01c0, PIN_INPUT,  2) /* (AF13) .I2C3_SCL */
			AM65X_IOPAD(0x01d4, PIN_INPUT,  2) /* (AG12) .I2C3_SDA */
		>;
	};

	main_spi0_pins_default: main-spi0-pins-default {
		pinctrl-single,pins = <
			AM65X_IOPAD(0x01c4, PIN_INPUT,  0) /* (AH13) SPI0_CLK */
			AM65X_IOPAD(0x01c8, PIN_INPUT,  0) /* (AE13) SPI0_D0 */
			AM65X_IOPAD(0x01cc, PIN_INPUT,  0) /* (AD13) SPI0_D1 */
			AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */
		>;
	};

	main_mmc0_pins_default: main-mmc0-pins-default {
		pinctrl-single,pins = <
			AM65X_IOPAD(0x01a8, PIN_INPUT,  0) /* (B25) MMC0_CLK */
			AM65X_IOPAD(0x01ac, PIN_INPUT,  0) /* (B27) MMC0_CMD */
			AM65X_IOPAD(0x01a4, PIN_INPUT,  0) /* (A26) MMC0_DAT0 */
			AM65X_IOPAD(0x01a0, PIN_INPUT,  0) /* (E25) MMC0_DAT1 */
			AM65X_IOPAD(0x019c, PIN_INPUT,  0) /* (C26) MMC0_DAT2 */
			AM65X_IOPAD(0x0198, PIN_INPUT,  0) /* (A25) MMC0_DAT3 */
			AM65X_IOPAD(0x01b4, PIN_INPUT, 7) /* (A23) MMC0_SDCD */
			AM65X_IOPAD(0x01b0, PIN_INPUT,  0) /* (C25) MMC0_DS */
		>;
	};

	main_mmc1_pins_default: main-mmc1-pins-default {
		pinctrl-single,pins = <
			AM65X_IOPAD(0x02d4, PIN_INPUT,  0) /* (C27) MMC1_CLK */
			AM65X_IOPAD(0x02d8, PIN_INPUT,  0) /* (C28) MMC1_CMD */
			AM65X_IOPAD(0x02d0, PIN_INPUT,  0) /* (D28) MMC1_DAT0 */
			AM65X_IOPAD(0x02cc, PIN_INPUT,  0) /* (E27) MMC1_DAT1 */
			AM65X_IOPAD(0x02c8, PIN_INPUT,  0) /* (D26) MMC1_DAT2 */
			AM65X_IOPAD(0x02c4, PIN_INPUT,  0) /* (D27) MMC1_DAT3 */
			AM65X_IOPAD(0x02dc, PIN_INPUT,  0) /* (B24) MMC1_SDCD */
			AM65X_IOPAD(0x02e0, PIN_INPUT,  0) /* (C24) MMC1_SDWP */
		>;
	};

	pcie0_pins_default: pcie0-pins-default {
		pinctrl-single,pins = <
			AM65X_IOPAD(0x00b4, PIN_OUTPUT,  7) /* (AD17) GPIO0_45 (PERST1n) */
		>;
	};

	pcie1_pins_default: pcie1-pins-default {
		pinctrl-single,pins = <
			AM65X_IOPAD(0x00b8, PIN_OUTPUT,  7) /* (AH14) GPIO0_46 (PERST2n) */
		>;
	};

	phy1_pins_default: phy1-pins-default {
		pinctrl-single,pins = <
			AM65X_IOPAD(0x0210, PIN_OUTPUT, 7) /* (U27) GPIO1_36 Eth1_RSTn */
			AM65X_IOPAD(0x0238, PIN_INPUT,  7) /* (U26) GPIO1_46 (ETH1_ONn) */
		>;
	};

	phy2_pins_default: phy2-pins-default {
		pinctrl-single,pins = <
			AM65X_IOPAD(0x023c, PIN_OUTPUT, 7) /* (V25) GPIO1_47 Eth2_RSTn */
			AM65X_IOPAD(0x0240, PIN_INPUT,  7) /* (U24) GPIO1_48 (ETH2_ONn) */
		>;
	};

	phy3_pins_default: phy3-pins-default {
		pinctrl-single,pins = <
			AM65X_IOPAD(0x0288, PIN_OUTPUT, 7) /* (Y27) GPIO1_66 Eth3_RSTn */
			AM65X_IOPAD(0x028c, PIN_INPUT,  7) /* (Y26) GPIO1_67 (ETH3_ONn) */
		>;
	};

	usb1_pins_default: usb1-pins-default {
		pinctrl-single,pins = <
			AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
		>;
	};

	icssg0_mdio_pins_default: icssg0-mdio-pins-default {
		pinctrl-single,pins = <
			AM65X_IOPAD(0x0294, PIN_INPUT,  0) /* (AE26) PRG0_PRU0_GPO7.PRG0_MDIO0_MDIO */
			AM65X_IOPAD(0x0298, PIN_OUTPUT, 0) /* (AE28) PRG0_PRU1_GPO7.PRG0_MDIO0_MDC */
		>;
	};

	icssg0_mii_pins_default: icssg0-mii-pins-default {
		pinctrl-single,pins = <
			AM65X_IOPAD(0x01f4, PIN_INPUT,  1) /* (V24)  PRG0_PRU0_GPI0  RXD0 */
			AM65X_IOPAD(0x01f8, PIN_INPUT,  1) /* (W25)  PRG0_PRU0_GPI1  RXD1 */
			AM65X_IOPAD(0x01fc, PIN_INPUT,  1) /* (W24)  PRG0_PRU0_GPI2  RXD2 */
			AM65X_IOPAD(0x0200, PIN_INPUT,  1) /* (AA27) PRG0_PRU0_GPI3  RXD3 */
			AM65X_IOPAD(0x0204, PIN_INPUT,  1) /* (Y24)  PRG0_PRU0_GPI4  RXDV */
			AM65X_IOPAD(0x0208, PIN_INPUT,  1) /* (V28)  PRG0_PRU0_GPI5  RXER */
			AM65X_IOPAD(0x020c, PIN_INPUT,  1) /* (Y25)  PRG0_PRU0_GPI6  RX_CLK */
			AM65X_IOPAD(0x0214, PIN_INPUT,  1) /* (V27)  PRG0_PRU0_GPI8  RXLINK */
			AM65X_IOPAD(0x0218, PIN_INPUT,  1) /* (V26)  PRG0_PRU0_GPI9  COL */
			AM65X_IOPAD(0x021c, PIN_INPUT,  1) /* (U25)  PRG0_PRU0_GPI10 CRS */
			AM65X_IOPAD(0x0270, PIN_OUTPUT, 0) /* (AB24) PRG0_PRU1_GPO11 TXD0 */
			AM65X_IOPAD(0x0274, PIN_OUTPUT, 0) /* (AC25) PRG0_PRU1_GPO12 TXD1 */
			AM65X_IOPAD(0x0278, PIN_OUTPUT, 0) /* (AD25) PRG0_PRU1_GPO13 TXD2 */
			AM65X_IOPAD(0x027c, PIN_OUTPUT, 0) /* (AD24) PRG0_PRU1_GPO14 TXD3 */
			AM65X_IOPAD(0x0280, PIN_OUTPUT, 0) /* (AE27) PRG0_PRU1_GPO15 TXEN */
			AM65X_IOPAD(0x0284, PIN_INPUT,  1) /* (AC24) PRG0_PRU1_GPI16 TX_CLK */

			AM65X_IOPAD(0x0220, PIN_OUTPUT, 0) /* (AB25) PRG0_PRU0_GPO11 TXD0 */
			AM65X_IOPAD(0x0224, PIN_OUTPUT, 0) /* (AD27) PRG0_PRU0_GPO12 TXD1 */
			AM65X_IOPAD(0x0228, PIN_OUTPUT, 0) /* (AC26) PRG0_PRU0_GPO13 TXD2 */
			AM65X_IOPAD(0x022c, PIN_OUTPUT, 0) /* (AD26) PRG0_PRU0_GPO14 TXD3 */
			AM65X_IOPAD(0x0230, PIN_OUTPUT, 0) /* (AA24) PRG0_PRU0_GPO15 TXEN */
			AM65X_IOPAD(0x0234, PIN_INPUT,  1) /* (AD28) PRG0_PRU0_GPI16 TX_CLK */
			AM65X_IOPAD(0x0244, PIN_INPUT,  1) /* (AB28) PRG0_PRU1_GPI0  RXD0 */
			AM65X_IOPAD(0x0248, PIN_INPUT,  1) /* (AC28) PRG0_PRU1_GPI1  RXD1 */
			AM65X_IOPAD(0x024c, PIN_INPUT,  1) /* (AC27) PRG0_PRU1_GPI2  RXD2 */
			AM65X_IOPAD(0x0250, PIN_INPUT,  1) /* (AB26) PRG0_PRU1_GPI3  RXD3 */
			AM65X_IOPAD(0x0254, PIN_INPUT,  1) /* (AA25) PRG0_PRU1_GPI4  RXDV */
			AM65X_IOPAD(0x0258, PIN_INPUT,  1) /* (U23)  PRG0_PRU1_GPI5  RXER */
			AM65X_IOPAD(0x025c, PIN_INPUT,  1) /* (AB27) PRG0_PRU1_GPI6  RX_CLK */
			AM65X_IOPAD(0x0264, PIN_INPUT,  1) /* (W27)  PRG0_PRU1_GPI8  RXLINK */
			AM65X_IOPAD(0x0268, PIN_INPUT,  1) /* (Y28)  PRG0_PRU1_GPI9  COL */
			AM65X_IOPAD(0x026c, PIN_INPUT,  1) /* (AA28) PRG0_PRU1_GPI10 CRS */
		>;
	};

	icssg1_mdio_pins_default: icssg1-mdio-pins-default {
		pinctrl-single,pins = <
			AM65X_IOPAD(0x0180, PIN_INPUT,  0) /* (AD18) PRG1_MDIO0_MDIO */
			AM65X_IOPAD(0x0184, PIN_OUTPUT, 0) /* (AH18) PRG1_MDIO0_MDC */
		>;
	};

	icssg1_rgmii_pins_default: icssg1-rgmii-pins-default {
		pinctrl-single,pins = <
			AM65X_IOPAD(0x00e0, PIN_INPUT,  2) /* (AE22) PRG1_RGMII1_RD0 */
			AM65X_IOPAD(0x00e4, PIN_INPUT,  2) /* (AG24) PRG1_RGMII1_RD1 */
			AM65X_IOPAD(0x00e8, PIN_INPUT,  2) /* (AF23) PRG1_RGMII1_RD2 */
			AM65X_IOPAD(0x00ec, PIN_INPUT,  2) /* (AD21) PRG1_RGMII1_RD3 */
			AM65X_IOPAD(0x00f0, PIN_INPUT,  2) /* (AG23) PRG1_RGMII1_RX_CTL */
			AM65X_IOPAD(0x00f8, PIN_INPUT,  2) /* (AF22) PRG1_RGMII1_RXC */
			AM65X_IOPAD(0x010c, PIN_OUTPUT, 2) /* (AF21) PRG1_RGMII1_TX_CTL */
			AM65X_IOPAD(0x0110, PIN_OUTPUT, 2) /* (AH20) PRG1_RGMII1_TD0 */
			AM65X_IOPAD(0x0114, PIN_OUTPUT, 2) /* (AH21) PRG1_RGMII1_TD1 */
			AM65X_IOPAD(0x0118, PIN_OUTPUT, 2) /* (AG20) PRG1_RGMII1_TD2 */
			AM65X_IOPAD(0x011c, PIN_OUTPUT, 2) /* (AD19) PRG1_RGMII1_TD3 */
			AM65X_IOPAD(0x0120, PIN_INPUT,  2) /* (AD20) PRG1_RGMII1_TXC */
		>;
	};

	icssg2_mii_pins_default: icssg2-mii-pins-default {
		pinctrl-single,pins = <
			AM65X_IOPAD(0x0078, PIN_INPUT,  /*12*/1) /* (AF18) PRG2_PRU0_GPI0  RXD0 */
			AM65X_IOPAD(0x007c, PIN_INPUT,  /*12*/1) /* (AE18) PRG2_PRU0_GPI1  RXD1 */
			AM65X_IOPAD(0x0080, PIN_INPUT,  /*12*/1) /* (AH17) PRG2_PRU0_GPI2  RXD2 */
			AM65X_IOPAD(0x0084, PIN_INPUT,  /*12*/1) /* (AG18) PRG2_PRU0_GPI3  RXD3 */
			AM65X_IOPAD(0x0088, PIN_INPUT,  /*12*/1) /* (AG17) PRG2_PRU0_GPI4  RXDV */
			AM65X_IOPAD(0x008c, PIN_INPUT,  /*12*/1) /* (AF17) PRG2_PRU0_GPI5  RXER */
			AM65X_IOPAD(0x0090, PIN_INPUT,  /*12*/1) /* (AE17) PRG2_PRU0_GPI6  RX_CLK */
			AM65X_IOPAD(0x0098, PIN_INPUT,  /*12*/1) /* (AH16) PRG2_PRU0_GPI8  RXLINK */
			AM65X_IOPAD(0x00d8, PIN_OUTPUT, /*9*/0) /* (AD14) PRG2_PRU1_GPO11 TXD0 */
			AM65X_IOPAD(0x0030, PIN_OUTPUT, /*9*/3) /* (N26)  PRG2_PRU1_GPO12 TXD1 */
			AM65X_IOPAD(0x0034, PIN_OUTPUT, /*9*/3) /* (N25)  PRG2_PRU1_GPO13 TXD2 */
			AM65X_IOPAD(0x0038, PIN_OUTPUT, /*9*/3) /* (P24)  PRG2_PRU1_GPO14 TXD3 */
			AM65X_IOPAD(0x003c, PIN_OUTPUT, /*9*/3) /* (R27)  PRG2_PRU1_GPO15 TXEN */
			AM65X_IOPAD(0x00dc, PIN_INPUT,  /*12*/1) /* (AE14) PRG2_PRU1_GPI16 TX_CLK */
		>;
	};

	rtc_pins_default: rtc-pins-default {
		pinctrl-single,pins = <
			AM65X_IOPAD(0x009c, PIN_INPUT,  7) /* (AG16) GPIO0_39 RTC_INTn */
		>;
	};
};

&main_pmx1 {
	main_gpio1_1_pins_default: main-gpio1-1-pins-default {
		pinctrl-single,pins = <
			AM65X_IOPAD(0x0018, PIN_OUTPUT, 7) /* (B22) GPIO1_88 TP401 */
			AM65X_IOPAD(0x001c, PIN_OUTPUT, 7) /* (C23) GPIO1_89 TP402 */
		>;
	};

	main_i2c0_pins_default: main-i2c0-pins-default {
		pinctrl-single,pins = <
			AM65X_IOPAD(0x0000, PIN_INPUT,  0) /* (D20) I2C0_SCL */
			AM65X_IOPAD(0x0004, PIN_INPUT,  0) /* (C21) I2C0_SDA */
		>;
	};

	main_i2c1_pins_default: main-i2c1-pins-default {
		pinctrl-single,pins = <
			AM65X_IOPAD(0x0008, PIN_INPUT,  0) /* (B21) I2C1_SCL */
			AM65X_IOPAD(0x000c, PIN_INPUT,  0) /* (E21) I2C1_SDA */
		>;
	};
};

&main_gpio0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_gpio0_pins_default>;

        gpio0-3 {
                gpio-hog;
                gpios = <3 0>;
                output-high;
                line-name = "LED_RSTn";
        };

        gpio0-7 {
                gpio-hog;
                gpios = <7 0>;
                output-high;
                line-name = "eMMC_RSTn";
        };

        gpio0-11 {
                gpio-hog;
                gpios = <11 0>;
                output-high;
                line-name = "USB_RSTn";
        };

	/* @todo pulse low at startup? */
	gpio0-44 {
                gpio-hog;
                gpios = <44 0>;
                output-high;
                line-name = "I2C_RESETn";
	};
};

&main_gpio1 {
	pinctrl-names = "default";
	pinctrl-0 = </*&main_gpio1_pins_default*/ &main_gpio1_1_pins_default>;

	gpio1-88 {
                gpio-hog;
                gpios = <88 0>;
                output-low;
                line-name = "TP401";
	};

	gpio1-89 {
                gpio-hog;
                gpios = <89 0>;
                output-low;
                line-name = "TP402";
	};
};

&wkup_gpio0 {
	pinctrl-names = "default";
	pinctrl-0 = <&wkup_gpio0_pins_default>;

	gpio0-10 {
                gpio-hog;
                gpios = <10 0>;
                output-low;
                line-name = "TP501";
	};

	gpio0-11 {
                gpio-hog;
                gpios = <11 0>;
                output-low;
                line-name = "TP502";
	};
};

&wkup_uart0 {
	/* Wakeup UART is used by System firmware */
	status = "reserved";
};

&main_uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart0_pins_default>;
	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};

&wkup_i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&wkup_i2c0_pins_default>;
	clock-frequency = <400000>;
};

&mcu_i2c0 {
	clock-frequency = <100000>;
	status = "disabled"; /* pull-up removed from protos */
/* @todo
        usb2517i@2c {
                compatible = "microchip,usb2517i";
                reg = <0x2c>;
                reset-gpios = <&main_gpio0 11 GPIO_ACTIVE_LOW>;
        };
*/
};

&mcu_spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_spi0_pins_default>;
	ti,pindir-d0-out-d1-in = <1>;
	ti,spi-num-cs = <4>;
};

&main_i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c0_pins_default>;
	clock-frequency = <400000>;

	gpio_expander: gpio@74 {
		compatible = "nxp,pca9539";
		reg = <0x74>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&main_gpio0>;
		interrupts = <43 IRQ_TYPE_EDGE_FALLING>;
		vcc-supply = <&vcc3v3_io>;
	};
};

&main_i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c1_pins_default>;
	clock-frequency = <400000>;
};

&main_i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c2_pins_default>;
	clock-frequency = <400000>;

        adc128d818@35 {
                compatible = "ti,adc128d818";
                reg = <0x35>;
                ti,mode = /bits/ 8 <1>;
		interrupts-extended = <&gpio_expander 14 IRQ_TYPE_EDGE_FALLING>;
        };

	sensor@48 {
		compatible = "nxp,pct2075";
		reg = <0x48>;
		vs-supply = <&vcc3v3_io>;
	};

	leds: leds@60 {
		compatible = "ti,tlc59116";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x60>;

	        front0b@0 {
	                label = "front:blue:0";
			reg = <0x0>;
		};

	        front0g@1 {
	                label = "front:green:0";
		reg = <0x1>;
		};

	        front0r@2 {
	                label = "front:red:0";
		        reg = <0x2>;
		};

	        front1b@3 {
	                label = "front:blue:1";
		        reg = <0x3>;
		};

	        front1g@4 {
	                label = "front:green:1";
		        reg = <0x4>;
		};

	        front1r@5 {
	                label = "front:red:1";
		        reg = <0x5>;
		};

	        front2b@6 {
	                label = "front:blue:2";
		        reg = <0x6>;
		};

	        front2g@7 {
	                label = "front:green:2";
		        reg = <0x7>;
		};

	        front2r@8 {
	                label = "front:red:2";
		        reg = <0x8>;
		};

	        front3b@9 {
	                label = "front:blue:3";
		        reg = <0x9>;
		};

	        front3g@a {
	                label = "front:green:3";
		        reg = <0xa>;
		};

	        front3r@b {
	                label = "front:red:3";
		        reg = <0xb>;
		};

	        front4g@c {
	                label = "front:green:4";
		        reg = <0xc>;
		};

	        front4r@d {
	                label = "front:red:4";
		        reg = <0xd>;
		};

	        front5g@e {
	                label = "front:green:5";
		        reg = <0xe>;
		};

	        front5r@f {
	                label = "front:red:5";
		        reg = <0xf>;
		};
	};

        rtc@6f {
                compatible = "isil,isl12022";
                reg = <0x6f>;
		pinctrl-names = "default";
		pinctrl-0 = <&rtc_pins_default>;
		interrupts-extended = <&main_gpio0 39 IRQ_TYPE_EDGE_FALLING>;
		aux-voltage-chargeable = <0>;
        };
};

&main_i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c3_pins_default>;
	clock-frequency = <400000>;
};

&main_spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_spi0_pins_default>;
	ti,pindir-d0-out-d1-in = <1>;
};

/* @todo fix/remove? */
&sdhci0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_mmc0_pins_default>;
	bus-width = <4>;
	non-removable;
	ti,driver-strength-ohm = <50>;
	disable-wp;
	vqmmc-supply = <&vcc3v3_io>;
/*
	no-1-8-v;
	sdhci-caps-mask = <0x60040000 0x90000000>;
	sdhci-caps = <0x40000000 0x00000000>;
*/
	status = "disabled";
	max-frequency = <25000000>;
/*
	mmc-pwrseq = <&sdhci0_pwrseq>;
*/
};

&sdhci1 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_mmc1_pins_default>;
	ti,driver-strength-ohm = <50>;
	bus-width = <4>;
	vqmmc-supply = <&vcc3v3_io>;
	no-1-8-v;
	/*
	LJO change: was
	max-frequency = <49950000>;
	*/
	max-frequency = <10000000>;
};

&dwc3_0 {
	clocks = <&k3_clks 151 2>;
	assigned-clocks = <&k3_clks 151 2>;
	assigned-clock-parents = <&k3_clks 151 4>;
};

&usb0 {
	dr_mode = "host";
};

&usb1 {
	pinctrl-names = "default";
	pinctrl-0 = <&usb1_pins_default>;
	dr_mode = "host";
};

&pcie0_rc {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie0_pins_default>;
	device_type = "pci";
        num-lanes = <1>;
        phys = <&serdes0 PHY_TYPE_PCIE 1>;
        phy-names = "pcie-phy0";
	reset-gpios = <&main_gpio0 45 GPIO_ACTIVE_LOW>;
	max-link-speed = <1>;
	/*
	Offer CPM
	LJO change
	was:
        status = "okay";
	*/
    status = "disabled";
};

&pcie1_rc {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie1_pins_default>;
	device_type = "pci";
        num-lanes = <1>;
        phys = <&serdes1 PHY_TYPE_PCIE 0>;
        phy-names = "pcie-phy0";
	reset-gpios = <&main_gpio0 46 GPIO_ACTIVE_LOW>;
	max-link-speed = <1>;
	/*
	LJO change
	was:
        status = "okay";
	*/
    status = "disabled";
};

&pru0_0 {
	firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf";
};

&rtu0_0 {
	firmware-name = "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf";
};

&tx_pru0_0 {
	firmware-name = "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf";
};

&pru0_1 {
	firmware-name = "ti-pruss/am65x-sr2-pru1-prueth-fw.elf";
};

&rtu0_1 {
	firmware-name = "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf";
};

&tx_pru0_1 {
	firmware-name = "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
};

&pru1_0 {
	firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf";
};

&rtu1_0 {
	firmware-name = "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf";
};

&tx_pru1_0 {
	firmware-name = "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf";
};

&pru2_0 {
	firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf";
};

&rtu2_0 {
	firmware-name = "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf";
};

&tx_pru2_0 {
	firmware-name = "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf";
};

&icssg0_mdio {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&icssg0_mdio_pins_default>;

	/* DP83822 on Eth1 */
	icssg0_phy0: ethernet-phy@1 {
		reg = <1>;

		interrupts-extended = <&main_gpio1 46 IRQ_TYPE_LEVEL_LOW>;
/*
		interrupt-parent = <&main_gpio1>;
		interrupts = <36 GPIO_ACTIVE_LOW>;
*/
		pinctrl-names = "default";
		pinctrl-0 = <&phy1_pins_default>;
		reset-names = "phy";
		reset-gpios = <&main_gpio1 36 GPIO_ACTIVE_LOW>;
		reset-assert-us = <10>;
		reset-deassert-us = <2000>;

		rx-internal-delay-ps = <3500>;
		tx-internal-delay-ps = <3500>;

	};

	/* DP83822 on Eth2 */
	icssg0_phy1: ethernet-phy@2 {
		reg = <2>;

		interrupts-extended = <&main_gpio1 48 IRQ_TYPE_LEVEL_LOW>;
/*
		interrupt-parent = <&main_gpio1>;
		interrupts = <47 GPIO_ACTIVE_LOW>;
*/
		pinctrl-names = "default";
		pinctrl-0 = <&phy2_pins_default>;
		reset-names = "phy";
		reset-gpios = <&main_gpio1 47 GPIO_ACTIVE_LOW>;
		reset-assert-us = <10>;
		reset-deassert-us = <2000>;

		rx-internal-delay-ps = <3500>;
		tx-internal-delay-ps = <3500>;

	};
};

&icssg1_mdio {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&icssg1_mdio_pins_default>;

	/* DP83867 on Eth3 */
	icssg1_phy0: ethernet-phy-ieee802.3-c45@3 {
		reg = <3>;

		interrupts-extended = <&main_gpio1 67 IRQ_TYPE_EDGE_FALLING>;
		pinctrl-names = "default";
		pinctrl-0 = <&phy3_pins_default>;
		reset-names = "phy";
		reset-gpios = <&main_gpio1 66 GPIO_ACTIVE_LOW>;
		reset-assert-us = <1>;
		reset-deassert-us = <195>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
	};
};

此致、

丹尼尔

0 admin 1 年多前

TI__Guru**** 657500 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

好的、我找到了一些关于通道移位的背景、但仍然不清楚它仅适用于 SR1器件。 Linux 和 MII 不是主要用例(RGMII 用于 Linux、MII 用于 EtherCAT 等)、因此可能会错误地保留内容。

佩卡

0 admin 1 年多前

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请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

当使用 MII 时、我可以确认 AM65x 和 AM64x 中是否需要进行通道移位。

有一个类似的案例 https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1083319/am6548-how-to-customize-the-phy-setting-in-pru-ethernet/4036304#4036304 . POST 没有.dts 补丁文件、但我要将其附加在这里。它用于 ICSSG1。我还将与该调试的相关人员进行核实、以便了解详情。

e2e.ti.com/.../0001_2D00_arm64_2D00_dts_2D00_ti_2D00_k3_2D00_am65_2D00_Add_2D00_support_2D00_for_2D00_MII.patch

佩卡

0 admin 1 年多前

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请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

好的、谢谢。

我见过几个关于 AM65x 上 MII 模式的其他线程、但都没有发现已结束、没有找到适用的解决方案。

BTW 我们没有看门狗超时问题、但什么都没有。

已比较 DTS 文件。我们没有看到任何明显错误的地方。

等您的下一个提示。

0 admin 1 年多前

TI__Guru**** 657500 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

MII 测试是使用 https://www.ti.com/lit/pdf/spruim6 第7.1节中所述的"默认"引脚多路复用完成的。 "备用"引脚多路复用(第7.2节)尚未使用 MII 和最新的 ICSSG 固件进行测试。我们仍在研究这个问题、但我想发送这个问题、以防它有助于您继续操作。

佩卡

0 admin 1 年多前

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请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

我是 Daniel Marmier 的同事。

我采用了您的开发套件 TMDX654IDKEVM、并使用您的预编译引导加载程序/kernel/rootfs 进行了引导。
我之前通过按照 IDK 架构中所述安装/卸载一些电阻器、对2个 MII 接口中的2个 RGMII 接口进行了转换。
最后、我按如下方式更改 idk 器件树：
diff --git a/arch/arm64/boot/dts/ti/k3-am654-idk.dts b/arch/arm64/boot/dts/ti/k3-am654-idk.dts
索引6170d7ea0f0c..7121ebbc174f 100644
--a/arch/arm64/boot/dts/ti/k3-am654-idk.dts
++ b/arch/arm64/boot/dts/ti/k3-am654-idk.dts
@@-90、7 +90、7 @@ icssg0_eth: icssg0-eth {

icssg0_emac0：Ethernet-mii0｛
PHY-Handle =<&icssg0_phy0>；
- phy-mode ="rgmII-rxid"；
+ phy-mode ="MII"；
SYSCON-RGMII-DELAY =<&SCM_conf 0x4100>；
/*由引导加载程序填充*/
local-mac-address =[00 00 00 00 00 00]；
@@-98、7 + 98、7 @@ icssg0_emac0：Ethernet-mii0｛

icssg0_emac1：Ethernet-mii1｛
PHY-Handle =<&icssg0_phy1>；
- phy-mode ="rgmII-rxid"；
+ phy-mode ="MII"；
SYSCON-RGMII-DELAY =<&SCM_conf 0x4104>；
/*由引导加载程序填充*/
local-mac-address =[00 00 00 00 00 00]；
@@-195、31 + 195、33 @@ AM65X_IOPAD (0x0298、PIN_OUTPUT、0)/*(AE28) PRG0_MDIO0_MDC */

icssg0_RGMII_PINS_DEFAULT：icssg0-RGMII-PINS-DEFAULT｛
PINCCTRL-SINGLE、PINS =<
- AM65X_IOPAD (0x0244、PIN_INPUT、2)/*(AB28) PRG0_PRU1_GPO0.PRG0_RGMII2_RD0 */
- AM65X_IOPAD (0x0248、PIN_INPUT、2)/*(AC28) PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */
- AM65X_IOPAD (0x024c、PIN_INPUT、2)/*(AC27) PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */
- AM65X_IOPAD (0x0250、PIN_INPUT、2)/*(AB26) PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */
- AM65X_IOPAD (0x0274、PIN_OUTPUT、2)/*(AC25) PRG0_PRU1_GPO12.PRG0_RGMII2_TD0 */
- AM65X_IOPAD (0x0278、PIN_OUTPUT、2)/*(AD25) PRG0_PRU1_GPO13.PRG0_RGMII2_TD1 */
- AM65X_IOPAD (0x027c、PIN_OUTPUT、2)/*(AD24) PRG0_PRU1_GPO14.PRG0_RGMII2_TD2 */
- AM65X_IOPAD (0x0280、PIN_OUTPUT、2)/*(AE27) PRG0_PRU1_GPO15.PRG0_RGMII2_TD3 */
- AM65X_IOPAD (0x0284、PIN_INPUT、2)/*(AC24) PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */
- AM65X_IOPAD (0x0270、PIN_OUTPUT、2)/*(AB24) PRG0_PRU1_GPO11.PRG0_RGMII2_TX_CTL */
- AM65X_IOPAD (0x025c、PIN_INPUT、2)/*(AB27) PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */
- AM65X_IOPAD (0x025c、PIN_INPUT、2)/*(AB27) PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */
- AM65X_IOPAD (0x0254、PIN_INPUT、2)/*(AA25) PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */
-
- AM65X_IOPAD (0x01f4、PIN_INPUT、2)/*(V24) PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */
- AM65X_IOPAD (0x01f8、PIN_INPUT、2)/*(W25) PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */
- AM65X_IOPAD (0x01fc、PIN_INPUT、2)/*(W24) PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */
- AM65X_IOPAD (0x0200、PIN_INPUT、2)/*(AA27) PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */
- AM65X_IOPAD (0x0224、PIN_OUTPUT、2)/*(AD27) PRG0_PRU0_GPO12.PRG0_RGMII1_TD0 */
- AM65X_IOPAD (0x0228、PIN_OUTPUT、2)/*(AC26) PRG0_PRU0_GPO13.PRG0_RGMII1_TD1 */
- AM65X_IOPAD (0x0248、PIN_INPUT、2)/*(AC28) PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */
- AM65X_IOPAD (0x024c、PIN_INPUT、2)/*(AC27) PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */
- AM65X_IOPAD (0x0250、PIN_INPUT、2)/*(AB26) PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */
- AM65X_IOPAD (0x0274、PIN_OUTPUT、2)/*(AC25) PRG0_PRU1_GPO12.PRG0_RGMII2_TD0 */
- AM65X_IOPAD (0x0278、PIN_OUTPUT、2)/*(AD25) PRG0_PRU1_GPO13.PRG0_RGMII2_TD1 */
- AM65X_IOPAD (0x027c、PIN_OUTPUT、2)/*(AD24) PRG0_PRU1_GPO14.PRG0_RGMII2_TD2 */
- AM65X_IOPAD (0x0280、PIN_OUTPUT、2)/*(AE27) PRG0_PRU1_GPO15.PRG0_RGMII2_TD3 */
- AM65X_IOPAD (0x0284、PIN_INPUT、2)/*(AC24) PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */
- AM65X_IOPAD (0x0270、PIN_OUTPUT、2)/*(AB24) PRG0_PRU1_GPO11.PRG0_RGMII2_TX_CTL */
- AM65X_IOPAD (0x025c、PIN_INPUT、2)/*(AB27) PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */
- AM65X_IOPAD (0x0254、PIN_INPUT、2)/*(AA25) PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */
-
- AM65X_IOPAD (0x01f4、PIN_INPUT、2)/*(V24) PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */
- AM65X_IOPAD (0x01f8、PIN_INPUT、2)/*(W25) PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */
- AM65X_IOPAD (0x01fc、PIN_INPUT、2)/*(W24) PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */
- AM65X_IOPAD (0x0200、PIN_INPUT、2)/*(AA27) PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */
- AM65X_IOPAD (0x0224、PIN_OUTPUT、2)/*(AD27) PRG0_PRU0_GPO12.PRG0_RGMII1_TD0 */
- AM65X_IOPAD (0x0228、PIN_OUTPUT、2)/*(AC26) PRG0_PRU0_GPO13.PRG0_RGMII1_TD1 */
- AM65X_IOPAD (0x022c、PIN_OUTPUT、2)/*(AD26) PRG0_PRU0_GPO14.PRG0_RGMII1_TD2 */
- AM65X_IOPAD (0x0230、PIN_OUTPUT、2)/*(AA24) PRG0_PRU0_GPO15.PRG0_RGMII1_TD3 */
- AM65X_IOPAD (0x0234、PIN_INPUT、2)/*(AD28) PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */
- AM65X_IOPAD (0x0220、PIN_OUTPUT、2)/*(AB25) PRG0_PRU0_GPO11.PRG0_RGMII1_TX_CTL */
- AM65X_IOPAD (0x020c、PIN_INPUT、2)/*(Y25) PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */
- AM65X_IOPAD (0x0204、PIN_INPUT、2)/*(Y24) PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */
+ AM65X_IOPAD (0x01f4、PIN_INPUT、1)/*(V24) PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */
+ AM65X_IOPAD (0x01f8、PIN_INPUT、1)/*(W25) PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */
+ AM65X_IOPAD (0x01fc、PIN_INPUT、1)/*(W24) PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */
+ AM65X_IOPAD (0x0200、PIN_INPUT、1)/*(AA27) PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */
+ AM65X_IOPAD (0x0204、PIN_INPUT、1)/*(Y24) PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */
+ AM65X_IOPAD (0x0208、PIN_INPUT、1)/*(V28) PRG0_PRU0_GPI5 RXER */
+ AM65X_IOPAD (0x020c、PIN_INPUT、1)/*(Y25) PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */
+ AM65X_IOPAD (0x0220、PIN_OUTPUT、0)/*(AB25) PRG0_PRU0_GPO11.PRG0_RGMII1_TX_CTL */
+ AM65X_IOPAD (0x0224、PIN_OUTPUT、0)/*(AD27) PRG0_PRU0_GPO12.PRG0_RGMII1_TD0 */
+ AM65X_IOPAD (0x0228、PIN_OUTPUT、0)/*(AC26) PRG0_PRU0_GPO13.PRG0_RGMII1_TD1 */
+ AM65X_IOPAD (0x022c、PIN_OUTPUT、0)/*(AD26) PRG0_PRU0_GPO14.PRG0_RGMII1_TD2 */
+ AM65X_IOPAD (0x0230、PIN_OUTPUT、0)/*(AA24) PRG0_PRU0_GPO15.PRG0_RGMII1_TD3 */
+ AM65X_IOPAD (0x0234、PIN_INPUT、1)/*(AD28) PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */
+
+ AM65X_IOPAD (0x0270、PIN_OUTPUT、0)/*(AB24) PRG0_PRU1_GPO11.PRG0_RGMII2_TX_CTL */
+ AM65X_IOPAD (0x0274、PIN_OUTPUT、0)/*(AC25) PRG0_PRU1_GPO12.PRG0_RGMII2_TD0 */
+ AM65X_IOPAD (0x0278、PIN_OUTPUT、0)/*(AD25) PRG0_PRU1_GPO13.PRG0_RGMII2_TD1 */
+ AM65X_IOPAD (0x027c、PIN_OUTPUT、0)/*(AD24) PRG0_PRU1_GPO14.PRG0_RGMII2_TD2 */
+ AM65X_IOPAD (0x0280、PIN_OUTPUT、0)/*(AE27) PRG0_PRU1_GPO15.PRG0_RGMII2_TD3 */
+ AM65X_IOPAD (0x0284、PIN_INPUT、1)/*(AC24) PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */
+ AM65X_IOPAD (0x0244、PIN_INPUT、1)/*(AB28) PRG0_PRU1_GPO0.PRG0_RGMII2_RD0 */
+ AM65X_IOPAD (0x0248、PIN_INPUT、1)/*(AC28) PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */
+ AM65X_IOPAD (0x024c、PIN_INPUT、1)/*(AC27) PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */
+ AM65X_IOPAD (0x0250、PIN_INPUT、1)/*(AB26) PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */
+ AM65X_IOPAD (0x0254、PIN_INPUT、1)/*(AA25) PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */
+ AM65X_IOPAD (0x0258、PIN_INPUT、1)/*(U23) PRG0_PRU1_GPI5 RXER */
+ AM65X_IOPAD (0x025c、PIN_INPUT、1)/*(AB27) PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */
>；
}；

我现在可以确认2个相关的 MII 接口正在工作。

与我们自己的硬件板相比、唯一的区别是 TX 线被交换到相反的 PRU 切片、如 MII 模式中所述。

能否确认交换工作正常？

此致、

劳伦特

0 admin 10 个月前

TI__Guru**** 657500 points

请注意，本文内容源自机器翻译，可能存在语法或其它翻译错误，仅供参考。如需获取准确内容，请参阅链接中的英语原文或自行翻译。

与我们自己的硬件板相比、唯一的区别是 TX 线被交换到相反的 PRU 切片、如 MII 模式中所述。

能否确认交换工作正常？
[/报价]
是的、需要换用。

处理器（参考译文帖）

处理器（参考译文帖）(Read Only)

[参考译文] AM6548：icssg_prueth 不在 MII 模式下传输