[参考译文] TDA4VM：TDA4VM EHRPWM4问题

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这是我的 dtsi 文件

// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for J721E SoC Family Main Domain peripherals
 *
 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
 */
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/mux/mux.h>
#include <dt-bindings/mux/ti-serdes.h>

/ {
	cmn_refclk: cmn-refclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	cmn_refclk1: cmn-refclk1 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};
};

&cbass_main {
	msmc_ram: sram@70000000 {
		compatible = "mmio-sram";
		reg = <0x0 0x70000000 0x0 0x800000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x70000000 0x800000>;

		atf-sram@0 {
			reg = <0x0 0x20000>;
		};
	};

	scm_conf: scm-conf@100000 {
		compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
		reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x00100000 0x1c000>;

		serdes_ln_ctrl: mux@4080 {
			compatible = "mmio-mux";
			reg = <0x00004080 0x50>;
			#mux-control-cells = <1>;
			/* Delete the serdes0 for POSEIDON, it will config in freertos. by hunagl1383, 2022/5/22 */
			mux-reg-masks = 
			        <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
					<0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
					<0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
					<0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
					/* SERDES4 lane0/1/2/3 select */
			idle-states = <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
				      <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>,
				      <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>,
				      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
				      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
		};

		usb_serdes_mux: mux-controller@4000 {
			compatible = "mmio-mux";
			#mux-control-cells = <1>;
			mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
					<0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
	    };
		ehrpwm_tbclk: clock@4140 {
			compatible = "ti,am654-ehrpwm-tbclk", "syscon";
			reg = <0x4140 0x18>;
			#clock-cells = <1>;
		};
	};

	ehrpwm0: pwm@3000000 {
			compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
			#pwm-cells = <3>;
			reg = <0x0 0x3000000 0x0 0x100>;
			power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
			clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>;
			clock-names = "tbclk", "fck";
	};

	ehrpwm1: pwm@3010000 {
			compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
			#pwm-cells = <3>;
			reg = <0x0 0x3010000 0x0 0x100>;
			power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
			clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>;
			clock-names = "tbclk", "fck";
	};

	ehrpwm2: pwm@3020000 {
			compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
			#pwm-cells = <3>;
			reg = <0x0 0x3020000 0x0 0x100>;
			power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
			clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>;
			clock-names = "tbclk", "fck";
	};

	ehrpwm3: pwm@3030000 {
			compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
			#pwm-cells = <3>;
			reg = <0x0 0x3030000 0x0 0x100>;
			power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
			clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>;
			clock-names = "tbclk", "fck";
	};

	ehrpwm4: pwm@3040000 {
			compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
			#pwm-cells = <3>;
			reg = <0x0 0x3040000 0x0 0x100>;
			power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
			clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>;
			clock-names = "tbclk", "fck";
	};

	ehrpwm5: pwm@3050000 {
			compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
			#pwm-cells = <3>;
			reg = <0x0 0x3050000 0x0 0x100>;
			power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
			clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>;
			clock-names = "tbclk", "fck";
	};

	main_ecap0: pwm@3100000 {
		compatible = "ti,am3352-ecap", "ti,am33xx-ecap";
		#pwm-cells = <3>;
		reg = <0x0 0x3100000 0x0 0x60>;
		power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 80 0>;
		clock-names = "fck";
	};

	gic500: interrupt-controller@1800000 {
		compatible = "arm,gic-v3";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
		      <0x00 0x01900000 0x00 0x100000>;	/* GICR */

		/* vcpumntirq: virtual CPU interface maintenance interrupt */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		gic_its: msi-controller@1820000 {
			compatible = "arm,gic-v3-its";
			reg = <0x00 0x01820000 0x00 0x10000>;
			socionext,synquacer-pre-its = <0x1000000 0x400000>;
			msi-controller;
			#msi-cells = <1>;
		};
	};

	main_gpio_intr: interrupt-controller0 {
		compatible = "ti,sci-intr";
		ti,intr-trigger-type = <1>;
		interrupt-controller;
		interrupt-parent = <&gic500>;
		#interrupt-cells = <1>;
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <131>;
		ti,interrupt-ranges = <8 392 56>;
	};

	main-navss {
		compatible = "simple-mfd";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		dma-coherent;
		dma-ranges;

		ti,sci-dev-id = <199>;

		main_navss_intr: interrupt-controller1 {
			compatible = "ti,sci-intr";
			ti,intr-trigger-type = <4>;
			interrupt-controller;
			interrupt-parent = <&gic500>;
			#interrupt-cells = <1>;
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <213>;
			ti,interrupt-ranges = <0 64 64>,
					      <64 448 64>,
					      <128 672 64>;
		};

		main_udmass_inta: interrupt-controller@33d00000 {
			compatible = "ti,sci-inta";
			reg = <0x0 0x33d00000 0x0 0x100000>;
			interrupt-controller;
			interrupt-parent = <&main_navss_intr>;
			msi-controller;
			#interrupt-cells = <0>;
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <209>;
			ti,interrupt-ranges = <0 0 256>;
		};

		secure_proxy_main: mailbox@32c00000 {
			compatible = "ti,am654-secure-proxy";
			#mbox-cells = <1>;
			reg-names = "target_data", "rt", "scfg";
			reg = <0x00 0x32c00000 0x00 0x100000>,
			      <0x00 0x32400000 0x00 0x100000>,
			      <0x00 0x32800000 0x00 0x100000>;
			interrupt-names = "rx_011";
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		};

		smmu0: iommu@36600000 {
			compatible = "arm,smmu-v3";
			reg = <0x0 0x36600000 0x0 0x100000>;
			interrupt-parent = <&gic500>;
			interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "eventq", "gerror";
			#iommu-cells = <1>;
		};

		hwspinlock: spinlock@30e00000 {
			compatible = "ti,am654-hwspinlock";
			reg = <0x00 0x30e00000 0x00 0x1000>;
			#hwlock-cells = <1>;
		};

		mailbox0_cluster0: mailbox@31f80000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f80000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster1: mailbox@31f81000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f81000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster2: mailbox@31f82000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f82000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster3: mailbox@31f83000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f83000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster4: mailbox@31f84000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f84000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster5: mailbox@31f85000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f85000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster6: mailbox@31f86000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f86000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster7: mailbox@31f87000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f87000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster8: mailbox@31f88000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f88000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster9: mailbox@31f89000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f89000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster10: mailbox@31f8a000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f8a000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster11: mailbox@31f8b000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f8b000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		main_ringacc: ringacc@3c000000 {
			compatible = "ti,am654-navss-ringacc";
			reg =	<0x0 0x3c000000 0x0 0x400000>,
				<0x0 0x38000000 0x0 0x400000>,
				<0x0 0x31120000 0x0 0x100>,
				<0x0 0x33000000 0x0 0x40000>;
			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
			ti,num-rings = <1024>;
			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <211>;
			msi-parent = <&main_udmass_inta>;
		};

		main_udmap: dma-controller@31150000 {
			compatible = "ti,j721e-navss-main-udmap";
			reg =	<0x0 0x31150000 0x0 0x100>,
				<0x0 0x34000000 0x0 0x100000>,
				<0x0 0x35000000 0x0 0x100000>;
			reg-names = "gcfg", "rchanrt", "tchanrt";
			msi-parent = <&main_udmass_inta>;
			#dma-cells = <1>;

			ti,sci = <&dmsc>;
			ti,sci-dev-id = <212>;
			ti,ringacc = <&main_ringacc>;

			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
						<0x0f>, /* TX_HCHAN */
						<0x10>; /* TX_UHCHAN */
			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
						<0x0b>, /* RX_HCHAN */
						<0x0c>; /* RX_UHCHAN */
			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
		};

		cpts@310d0000 {
			compatible = "ti,j721e-cpts";
			reg = <0x0 0x310d0000 0x0 0x400>;
			reg-names = "cpts";
			clocks = <&k3_clks 201 1>;
			clock-names = "cpts";
			interrupts-extended = <&main_navss_intr 391>;
			interrupt-names = "cpts";
			ti,cpts-periodic-outputs = <6>;
			ti,cpts-ext-ts-inputs = <8>;
		};
	};

	main_crypto: crypto@4e00000 {
		compatible = "ti,j721e-sa2ul";
		reg = <0x0 0x4e00000 0x0 0x1200>;
		power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;

		dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
				<&main_udmap 0x4001>;
		dma-names = "tx", "rx1", "rx2";
		dma-coherent;

		rng: rng@4e10000 {
			compatible = "inside-secure,safexcel-eip76";
			reg = <0x0 0x4e10000 0x0 0x7d>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&k3_clks 264 1>;
		};
	};

	main_pmx0: pinctrl@11c000 {
		compatible = "pinctrl-single";
		/* Proxy 0 addressing */
		reg = <0x0 0x11c000 0x0 0x2b4>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0xffffffff>;
	};

	serdes_wiz0: wiz@5000000 {
		compatible = "ti,j721e-wiz-16g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
		assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
		num-lanes = <2>;
		#reset-cells = <1>;
		ranges = <0x5000000 0x0 0x5000000 0x10000>;

		wiz0_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 292 11>, <&cmn_refclk>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz0_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 292 11>;
		};

		wiz0_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz0_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 292 0>;
		};

		wiz0_refclk_dig: refclk-dig {
			clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz0_refclk_dig>;
			assigned-clock-parents = <&k3_clks 292 11>;
		};

		wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
			clocks = <&wiz0_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz0_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes0: serdes@5000000 {
			compatible = "ti,sierra-phy-t0";
			reg-names = "serdes";
			reg = <0x5000000 0x10000>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;
			resets = <&serdes_wiz0 0>;
			reset-names = "sierra_reset";
			clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>;
			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll0_refclk", "pll1_refclk";
		};
	};

	serdes_wiz1: wiz@5010000 {
		compatible = "ti,j721e-wiz-16g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
		assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
		num-lanes = <2>;
		#reset-cells = <1>;
		ranges = <0x5010000 0x0 0x5010000 0x10000>;

		wiz1_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 293 13>, <&cmn_refclk>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz1_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 293 13>;
		};

		wiz1_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz1_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 293 0>;
		};

		wiz1_refclk_dig: refclk-dig {
			clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz1_refclk_dig>;
			assigned-clock-parents = <&k3_clks 293 13>;
		};

		wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{
			clocks = <&wiz1_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz1_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes1: serdes@5010000 {
			compatible = "ti,sierra-phy-t0";
			reg-names = "serdes";
			reg = <0x5010000 0x10000>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;
			resets = <&serdes_wiz1 0>;
			reset-names = "sierra_reset";
			clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>;
			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll0_refclk", "pll1_refclk";
		};
	};

	serdes_wiz2: wiz@5020000 {
		compatible = "ti,j721e-wiz-16g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
		assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
		num-lanes = <2>;
		#reset-cells = <1>;
		ranges = <0x5020000 0x0 0x5020000 0x10000>;

		wiz2_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 294 11>, <&cmn_refclk>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz2_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 294 11>;
		};

		wiz2_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz2_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 294 0>;
		};

		wiz2_refclk_dig: refclk-dig {
			clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz2_refclk_dig>;
			assigned-clock-parents = <&k3_clks 294 11>;
		};

		wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
			clocks = <&wiz2_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz2_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes2: serdes@5020000 {
			compatible = "ti,sierra-phy-t0";
			reg-names = "serdes";
			reg = <0x5020000 0x10000>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;
			resets = <&serdes_wiz2 0>;
			reset-names = "sierra_reset";
			clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>;
			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll0_refclk", "pll1_refclk";
		};
	};

	serdes_wiz3: wiz@5030000 {
		compatible = "ti,j721e-wiz-16g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
		assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
		num-lanes = <2>;
		#reset-cells = <1>;
		ranges = <0x5030000 0x0 0x5030000 0x10000>;

		wiz3_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 295 9>, <&cmn_refclk>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz3_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 295 9>;
		};

		wiz3_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz3_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 295 0>;
		};

		wiz3_refclk_dig: refclk-dig {
			clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
			#clock-cells = <0>;
			assigned-clocks = <&wiz3_refclk_dig>;
			assigned-clock-parents = <&k3_clks 295 9>;
		};

		wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
			clocks = <&wiz3_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz3_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes3: serdes@5030000 {
			compatible = "ti,sierra-phy-t0";
			reg-names = "serdes";
			reg = <0x5030000 0x10000>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;
			resets = <&serdes_wiz3 0>;
			reset-names = "sierra_reset";
			clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>;
			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll0_refclk", "pll1_refclk";
		};
	};
	/* disable the pcie0, conflict with serdes0. by huangl1383 2022/5/22 */
	pcie0_rc: pcie@2900000 {
		status="disabled";
		compatible = "ti,j721e-pcie-host";
		reg = <0x00 0x02900000 0x00 0x1000>,
		      <0x00 0x02907000 0x00 0x400>,
		      <0x00 0x0d000000 0x00 0x00800000>,
		      <0x00 0x10000000 0x00 0x00001000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 239 1>;
		clock-names = "fck";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xf>;
		vendor-id = <0x104c>;
		device-id = <0xb00d>;
		msi-map = <0x0 &gic_its 0x0 0x10000>;
		dma-coherent;
		ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
			 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie0_intc 0>, /* INT A */
				<0 0 0 2 &pcie0_intc 0>, /* INT B */
				<0 0 0 3 &pcie0_intc 0>, /* INT C */
				<0 0 0 4 &pcie0_intc 0>; /* INT D */

		pcie0_intc: interrupt-controller {
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupt-parent = <&gic500>;
			interrupts = <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>;
		};
	};

	pcie0_ep: pcie-ep@2900000 {
		status="disabled";
		compatible = "ti,j721e-pcie-ep";
		reg = <0x00 0x02900000 0x00 0x1000>,
		      <0x00 0x02907000 0x00 0x400>,
		      <0x00 0x0d000000 0x00 0x00800000>,
		      <0x00 0x10000000 0x00 0x08000000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
		ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 239 1>;
		clock-names = "fck";
		max-functions = /bits/ 8 <6>;
		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
		dma-coherent;
	};

	pcie1_rc: pcie@2910000 {
		compatible = "ti,j721e-pcie-host";
		reg = <0x00 0x02910000 0x00 0x1000>,
		      <0x00 0x02917000 0x00 0x400>,
		      <0x00 0x0d800000 0x00 0x00800000>,
		      <0x00 0x18000000 0x00 0x00001000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 240 1>;
		clock-names = "fck";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xf>;
		vendor-id = <0x104c>;
		device-id = <0xb00d>;
		msi-map = <0x0 &gic_its 0x10000 0x10000>;
		dma-coherent;
		ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
			 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
				<0 0 0 2 &pcie1_intc 0>, /* INT B */
				<0 0 0 3 &pcie1_intc 0>, /* INT C */
				<0 0 0 4 &pcie1_intc 0>; /* INT D */

		pcie1_intc: interrupt-controller {
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&gic500>;
			interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
		};
	};

	pcie1_ep: pcie-ep@2910000 {
		compatible = "ti,j721e-pcie-ep";
		reg = <0x00 0x02910000 0x00 0x1000>,
		      <0x00 0x02917000 0x00 0x400>,
		      <0x00 0x0d800000 0x00 0x00800000>,
		      <0x00 0x18000000 0x00 0x08000000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 240 1>;
		clock-names = "fck";
		max-functions = /bits/ 8 <6>;
		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
		dma-coherent;
	};

	pcie2_rc: pcie@2920000 {
		compatible = "ti,j721e-pcie-host";
		reg = <0x00 0x02920000 0x00 0x1000>,
		      <0x00 0x02927000 0x00 0x400>,
		      <0x00 0x0e000000 0x00 0x00800000>,
		      <0x44 0x00000000 0x00 0x00001000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 241 1>;
		clock-names = "fck";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xf>;
		vendor-id = <0x104c>;
		device-id = <0xb00d>;
		msi-map = <0x0 &gic_its 0x20000 0x10000>;
		dma-coherent;
		ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
			 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie2_intc 0>, /* INT A */
				<0 0 0 2 &pcie2_intc 0>, /* INT B */
				<0 0 0 3 &pcie2_intc 0>, /* INT C */
				<0 0 0 4 &pcie2_intc 0>; /* INT D */

		pcie2_intc: interrupt-controller {
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&gic500>;
			interrupts = <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>;
		};
	};

	pcie2_ep: pcie-ep@2920000 {
		compatible = "ti,j721e-pcie-ep";
		reg = <0x00 0x02920000 0x00 0x1000>,
		      <0x00 0x02927000 0x00 0x400>,
		      <0x00 0x0e000000 0x00 0x00800000>,
		      <0x44 0x00000000 0x00 0x08000000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
		ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 241 1>;
		clock-names = "fck";
		max-functions = /bits/ 8 <6>;
		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
		dma-coherent;
	};

	pcie3_rc: pcie@2930000 {
		compatible = "ti,j721e-pcie-host";
		reg = <0x00 0x02930000 0x00 0x1000>,
		      <0x00 0x02937000 0x00 0x400>,
		      <0x00 0x0e800000 0x00 0x00800000>,
		      <0x44 0x10000000 0x00 0x00001000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 242 1>;
		clock-names = "fck";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xf>;
		vendor-id = <0x104c>;
		device-id = <0xb00d>;
		msi-map = <0x0 &gic_its 0x30000 0x10000>;
		dma-coherent;
		ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
			 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie3_intc 0>, /* INT A */
				<0 0 0 2 &pcie3_intc 0>, /* INT B */
				<0 0 0 3 &pcie3_intc 0>, /* INT C */
				<0 0 0 4 &pcie3_intc 0>; /* INT D */

		pcie3_intc: interrupt-controller {
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&gic500>;
			interrupts = <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>;
		};
	};

	pcie3_ep: pcie-ep@2930000 {
		compatible = "ti,j721e-pcie-ep";
		reg = <0x00 0x02930000 0x00 0x1000>,
		      <0x00 0x02937000 0x00 0x400>,
		      <0x00 0x0e800000 0x00 0x00800000>,
		      <0x44 0x10000000 0x00 0x08000000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
		ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
		max-link-speed = <3>;
		num-lanes = <2>;
		power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 242 1>;
		clock-names = "fck";
		max-functions = /bits/ 8 <6>;
		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
		dma-coherent;
		#address-cells = <2>;
		#size-cells = <2>;
	};

	serdes_wiz4: wiz@5050000 {
		compatible = "ti,j721e-wiz-10g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 297 9>;
		assigned-clock-parents = <&k3_clks 297 10>;
		assigned-clock-rates = <19200000>;
		num-lanes = <4>;
		#reset-cells = <1>;
		ranges = <0x5050000 0x0 0x5050000 0x10000>,
			<0xa030a00 0x0 0xa030a00 0x40>;

		wiz4_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 297 9>, <&cmn_refclk>;
			clock-output-names = "wiz4_pll0_refclk";
			#clock-cells = <0>;
			assigned-clocks = <&wiz4_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 297 9>;
		};

		wiz4_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 297 9>, <&cmn_refclk>;
			clock-output-names = "wiz4_pll1_refclk";
			#clock-cells = <0>;
			assigned-clocks = <&wiz4_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 297 9>;
		};

		wiz4_refclk_dig: refclk-dig {
			clocks = <&k3_clks 297 9>, <&cmn_refclk>;
			clock-output-names = "wiz4_refclk_dig";
			#clock-cells = <0>;
			assigned-clocks = <&wiz4_refclk_dig>;
			assigned-clock-parents = <&k3_clks 297 9>;
		};

		wiz4_cmn_refclk_dig_div: cmn-refclk-dig-div {
			clocks = <&wiz4_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz4_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz4_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes4: serdes@5050000 {
			/*
			 * Note: we also map DPTX PHY registers as the Torrent
			 * needs to manage those.
			 */
			compatible = "ti,j721e-serdes-10g";
			reg = <0x5050000 0x10000>,
			      <0xa030a00 0x40>; /* DPTX PHY */
			reg-names = "torrent_phy", "dptx_phy";

			resets = <&serdes_wiz4 0>;
			reset-names = "torrent_reset";
			clocks = <&wiz4_pll0_refclk>;
			clock-names = "refclk";
			#address-cells = <1>;
			#size-cells = <0>;
			torrent_phy_dp: phy@0 {
				reg = <0>;
				resets = <&serdes_wiz4 1>;
				cdns,phy-type = <PHY_TYPE_DP>;
				cdns,num-lanes = <4>;
				cdns,max-bit-rate = <5400>;
				#phy-cells = <0>;
			};
		};
	};

	main_uart0: serial@2800000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02800000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 146 0>;
		clock-names = "fclk";
	};

	main_uart1: serial@2810000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02810000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 278 0>;
		clock-names = "fclk";
	};

	main_uart2: serial@2820000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02820000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <460800>;
		power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 279 0>;
		clock-names = "fclk";
	};

	main_uart3: serial@2830000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02830000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 280 0>;
		clock-names = "fclk";
	};

	main_uart4: serial@2840000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02840000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 281 0>;
		clock-names = "fclk";
	};

	main_uart5: serial@2850000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02850000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 282 0>;
		clock-names = "fclk";
	};

	main_uart6: serial@2860000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02860000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <460800>;
		power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 283 0>;
		clock-names = "fclk";
	};

	main_uart7: serial@2870000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02870000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 284 0>;
		clock-names = "fclk";
	};

	main_uart8: serial@2880000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02880000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 285 0>;
		clock-names = "fclk";
	};

	main_uart9: serial@2890000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02890000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 286 0>;
		clock-names = "fclk";
	};

	main_gpio0: gpio@600000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00600000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <256>, <257>, <258>, <259>,
			     <260>, <261>, <262>, <263>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <128>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 105 0>;
		clock-names = "gpio";
	};

	main_gpio1: gpio@601000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00601000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <288>, <289>, <290>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <36>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 106 0>;
		clock-names = "gpio";
	};

	main_gpio2: gpio@610000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00610000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <264>, <265>, <266>, <267>,
			     <268>, <269>, <270>, <271>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <128>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 107 0>;
		clock-names = "gpio";
	};

	main_gpio3: gpio@611000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00611000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <292>, <293>, <294>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <36>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 108 0>;
		clock-names = "gpio";
	};

	main_gpio4: gpio@620000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00620000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <272>, <273>, <274>, <275>,
			     <276>, <277>, <278>, <279>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <128>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 109 0>;
		clock-names = "gpio";
	};

	main_gpio5: gpio@621000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00621000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <296>, <297>, <298>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <36>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 110 0>;
		clock-names = "gpio";
	};

	main_gpio6: gpio@630000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00630000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <280>, <281>, <282>, <283>,
			     <284>, <285>, <286>, <287>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <128>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 111 0>;
		clock-names = "gpio";
	};

	main_gpio7: gpio@631000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x0 0x00631000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <300>, <301>, <302>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <36>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 112 0>;
		clock-names = "gpio";
	};

	main_sdhci0: mmc@4f80000 {
		compatible = "ti,j721e-sdhci-8bit";
		reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
		clock-names = "clk_ahb", "clk_xin";
		clocks = <&k3_clks 91 0>, <&k3_clks 91 1>;
		assigned-clocks = <&k3_clks 91 1>;
		assigned-clock-parents = <&k3_clks 91 2>;
		bus-width = <8>;
		mmc-hs400-1_8v;
		mmc-ddr-1_8v;
		ti,otap-del-sel-legacy = <0xf>;
		ti,otap-del-sel-mmc-hs = <0xf>;
		ti,otap-del-sel-ddr52 = <0x5>;
		ti,otap-del-sel-hs200 = <0x6>;
		ti,otap-del-sel-hs400 = <0x0>;
		ti,trm-icp = <0x8>;
		ti,strobe-sel = <0x77>;
		dma-coherent;
	};

	main_sdhci1: mmc@4fb0000 {
		compatible = "ti,j721e-sdhci-4bit";
		reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
		clock-names = "clk_ahb", "clk_xin";
		clocks = <&k3_clks 92 5>, <&k3_clks 92 0>;
		assigned-clocks = <&k3_clks 92 0>;
		assigned-clock-parents = <&k3_clks 92 1>;
		ti,otap-del-sel-legacy = <0x0>;
		ti,otap-del-sel-sd-hs = <0xf>;
		ti,otap-del-sel-sdr12 = <0xf>;
		ti,otap-del-sel-sdr25 = <0xf>;
		ti,otap-del-sel-sdr50 = <0xc>;
		ti,otap-del-sel-ddr50 = <0xc>;
		ti,trm-icp = <0x8>;
		ti,clkbuf-sel = <0x7>;
		dma-coherent;
	};

	main_sdhci2: mmc@4f98000 {
		compatible = "ti,j721e-sdhci-4bit";
		reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
		clock-names = "clk_ahb", "clk_xin";
		clocks = <&k3_clks 93 5>, <&k3_clks 93 0>;
		assigned-clocks = <&k3_clks 93 0>;
		assigned-clock-parents = <&k3_clks 93 1>;
		ti,otap-del-sel-legacy = <0x0>;
		ti,otap-del-sel-sd-hs = <0xf>;
		ti,otap-del-sel-sdr12 = <0xf>;
		ti,otap-del-sel-sdr25 = <0xf>;
		ti,otap-del-sel-sdr50 = <0xc>;
		ti,otap-del-sel-ddr50 = <0xc>;
		ti,trm-icp = <0x8>;
		ti,clkbuf-sel = <0x7>;
		dma-coherent;
	};

	usbss0: cdns-usb@4104000 {
		compatible = "ti,j721e-usb";
		reg = <0x00 0x4104000 0x00 0x100>;
		dma-coherent;
		power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
		clock-names = "ref", "lpm";
		assigned-clocks = <&k3_clks 288 15>;	/* USB2_REFCLK */
		assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		usb0: usb@6000000 {
			compatible = "cdns,usb3";
			reg = <0x00 0x6000000 0x00 0x10000>,
			      <0x00 0x6010000 0x00 0x10000>,
			      <0x00 0x6020000 0x00 0x10000>;
			reg-names = "otg", "xhci", "dev";
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
			interrupt-names = "host",
					  "peripheral",
					  "otg";
			maximum-speed = "super-speed";
			dr_mode = "otg";
		};
	};

	usbss1: cdns-usb@4114000 {
		compatible = "ti,j721e-usb";
		reg = <0x00 0x4114000 0x00 0x100>;
		dma-coherent;
		power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
		clock-names = "ref", "lpm";
		assigned-clocks = <&k3_clks 289 15>;	/* USB2_REFCLK */
		assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		usb1: usb@6400000 {
			compatible = "cdns,usb3";
			reg = <0x00 0x6400000 0x00 0x10000>,
			      <0x00 0x6410000 0x00 0x10000>,
			      <0x00 0x6420000 0x00 0x10000>;
			reg-names = "otg", "xhci", "dev";
			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
			interrupt-names = "host",
					  "peripheral",
					  "otg";
			maximum-speed = "super-speed";
			dr_mode = "otg";
		};
	};

	main_i2c0: i2c@2000000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2000000 0x0 0x100>;
		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 187 0>;
		power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
	};

	main_i2c1: i2c@2010000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2010000 0x0 0x100>;
		interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 188 0>;
		power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c2: i2c@2020000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2020000 0x0 0x100>;
		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 189 0>;
		power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c3: i2c@2030000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2030000 0x0 0x100>;
		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 190 0>;
		power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c4: i2c@2040000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2040000 0x0 0x100>;
		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 191 0>;
		power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c5: i2c@2050000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2050000 0x0 0x100>;
		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 192 0>;
		power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c6: i2c@2060000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2060000 0x0 0x100>;
		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 193 0>;
		power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
	};

	d5520: video-decoder@4300000 {
	       /* IMG D5520 driver configuration */
	       compatible = "img,d5500-vxd";
	       reg = <0x00 0x04300000 0x00 0x100000>;
	       power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
	       interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
	};
	
	vxe384: video-encoder@4200000 {
		compatible = "img,vxe384";
		reg = <0x00 0x04200000>,
		    <0x00 0x100000>;
		power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
		interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
	};
	ufs_wrapper: ufs-wrapper@4e80000 {
		compatible = "ti,j721e-ufs";
		reg = <0x0 0x4e80000 0x0 0x100>;
		power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 277 1>;
		assigned-clocks = <&k3_clks 277 1>;
		assigned-clock-parents = <&k3_clks 277 4>;
		ranges;
		#address-cells = <2>;
		#size-cells = <2>;

		ufs@4e84000 {
			compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
			reg = <0x0 0x4e84000 0x0 0x10000>;
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
			clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
			clock-names = "core_clk", "phy_clk", "ref_clk";
			dma-coherent;
		};
	};

	mhdp: dp-bridge@a000000 {
		compatible = "ti,j721e-mhdp8546";
		/*
		 * Note: we do not map DPTX PHY area, as that is handled by
		 * the PHY driver.
		 */
		reg = <0x0 0xa000000 0x0 0x30a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
		      <0x0 0x4f40000 0x0 0x20>;    /* DSS_EDP0_INTG_CFG_VP */
		reg-names = "mhdptx", "j721e-intg";

		clocks = <&k3_clks 151 36>;

		phys = <&torrent_phy_dp>;
		phy-names = "dpphy";

		interrupt-parent = <&gic500>;
		interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;

		power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;

		dp0_ports: ports {
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

	dss: dss@4a00000 {
		compatible = "ti,j721e-dss";
		reg =
			<0x00 0x04a00000 0x00 0x10000>, /* common_m */
			<0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
			<0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
			<0x00 0x04b10000 0x00 0x10000>, /* common_s2*/

			<0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
			<0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
			<0x00 0x04a50000 0x00 0x10000>, /* vid1 */
			<0x00 0x04a60000 0x00 0x10000>, /* vid2 */

			<0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
			<0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
			<0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
			<0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */

			<0x00 0x04a80000 0x00 0x10000>, /* vp1 */
			<0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
			<0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
			<0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
			<0x00 0x04af0000 0x00 0x10000>; /* wb */

		reg-names = "common_m", "common_s0",
			"common_s1", "common_s2",
			"vidl1", "vidl2","vid1","vid2",
			"ovr1", "ovr2", "ovr3", "ovr4",
			"vp1", "vp2", "vp3", "vp4",
			"wb";

		clocks =	<&k3_clks 152 0>,
				<&k3_clks 152 1>,
				<&k3_clks 152 4>,
				<&k3_clks 152 9>,
				<&k3_clks 152 13>;
		clock-names = "fck", "vp1", "vp2", "vp3", "vp4";

		power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;

		interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "common_m",
				  "common_s0",
				  "common_s1",
				  "common_s2";

		dss_ports: ports {
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

	mcasp0: mcasp@2b00000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b00000 0x0 0x2000>,
			<0x0 0x02b08000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 174 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp1: mcasp@2b10000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b10000 0x0 0x2000>,
			<0x0 0x02b18000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 175 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp2: mcasp@2b20000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b20000 0x0 0x2000>,
			<0x0 0x02b28000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 176 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp3: mcasp@2b30000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b30000 0x0 0x2000>,
			<0x0 0x02b38000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 177 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp4: mcasp@2b40000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b40000 0x0 0x2000>,
			<0x0 0x02b48000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 178 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp5: mcasp@2b50000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b50000 0x0 0x2000>,
			<0x0 0x02b58000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 179 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp6: mcasp@2b60000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b60000 0x0 0x2000>,
			<0x0 0x02b68000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 180 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp7: mcasp@2b70000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b70000 0x0 0x2000>,
			<0x0 0x02b78000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 181 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp8: mcasp@2b80000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b80000 0x0 0x2000>,
			<0x0 0x02b88000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 182 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp9: mcasp@2b90000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b90000 0x0 0x2000>,
			<0x0 0x02b98000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 183 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp10: mcasp@2ba0000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02ba0000 0x0 0x2000>,
			<0x0 0x02ba8000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 184 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp11: mcasp@2bb0000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02bb0000 0x0 0x2000>,
			<0x0 0x02bb8000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 185 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
	};

	watchdog0: watchdog@2200000 {
		compatible = "ti,j7-rti-wdt";
		reg = <0x0 0x2200000 0x0 0x100>;
		clocks = <&k3_clks 252 1>;
		power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
		assigned-clocks = <&k3_clks 252 1>;
		assigned-clock-parents = <&k3_clks 252 5>;
	};

	watchdog1: watchdog@2210000 {
		compatible = "ti,j7-rti-wdt";
		reg = <0x0 0x2210000 0x0 0x100>;
		clocks = <&k3_clks 253 1>;
		power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
		assigned-clocks = <&k3_clks 253 1>;
		assigned-clock-parents = <&k3_clks 253 5>;
	};

	main_r5fss0: r5fss@5c00000 {
		compatible = "ti,j721e-r5fss";
		ti,cluster-mode = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
			 <0x5d00000 0x00 0x5d00000 0x20000>;
		power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;

		main_r5fss0_core0: r5f@5c00000 {
			compatible = "ti,j721e-r5f";
			reg = <0x5c00000 0x00008000>,
			      <0x5c10000 0x00008000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <245>;
			ti,sci-proc-ids = <0x06 0xff>;
			resets = <&k3_reset 245 1>;
			firmware-name = "j7-main-r5f0_0-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};

		main_r5fss0_core1: r5f@5d00000 {
			compatible = "ti,j721e-r5f";
			reg = <0x5d00000 0x00008000>,
			      <0x5d10000 0x00008000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <246>;
			ti,sci-proc-ids = <0x07 0xff>;
			resets = <&k3_reset 246 1>;
			firmware-name = "j7-main-r5f0_1-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};
	};

	main_r5fss1: r5fss@5e00000 {
		compatible = "ti,j721e-r5fss";
		ti,cluster-mode = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
			 <0x5f00000 0x00 0x5f00000 0x20000>;
		power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;

		main_r5fss1_core0: r5f@5e00000 {
			compatible = "ti,j721e-r5f";
			reg = <0x5e00000 0x00008000>,
			      <0x5e10000 0x00008000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <247>;
			ti,sci-proc-ids = <0x08 0xff>;
			resets = <&k3_reset 247 1>;
			firmware-name = "j7-main-r5f1_0-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};

		main_r5fss1_core1: r5f@5f00000 {
			compatible = "ti,j721e-r5f";
			reg = <0x5f00000 0x00008000>,
			      <0x5f10000 0x00008000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <248>;
			ti,sci-proc-ids = <0x09 0xff>;
			resets = <&k3_reset 248 1>;
			firmware-name = "j7-main-r5f1_1-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};
	};

	c66_0: dsp@4d80800000 {
		compatible = "ti,j721e-c66-dsp";
		reg = <0x4d 0x80800000 0x00 0x00048000>,
		      <0x4d 0x80e00000 0x00 0x00008000>,
		      <0x4d 0x80f00000 0x00 0x00008000>;
		reg-names = "l2sram", "l1pram", "l1dram";
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <142>;
		ti,sci-proc-ids = <0x03 0xff>;
		resets = <&k3_reset 142 1>;
		firmware-name = "j7-c66_0-fw";
	};

	c66_1: dsp@4d81800000 {
		compatible = "ti,j721e-c66-dsp";
		reg = <0x4d 0x81800000 0x00 0x00048000>,
		      <0x4d 0x81e00000 0x00 0x00008000>,
		      <0x4d 0x81f00000 0x00 0x00008000>;
		reg-names = "l2sram", "l1pram", "l1dram";
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <143>;
		ti,sci-proc-ids = <0x04 0xff>;
		resets = <&k3_reset 143 1>;
		firmware-name = "j7-c66_1-fw";
	};

	c71_0: dsp@64800000 {
		compatible = "ti,j721e-c71-dsp";
		reg = <0x00 0x64800000 0x00 0x00080000>,
		      <0x00 0x64e00000 0x00 0x0000c000>;
		reg-names = "l2sram", "l1dram";
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <15>;
		ti,sci-proc-ids = <0x30 0xff>;
		resets = <&k3_reset 15 1>;
		firmware-name = "j7-c71_0-fw";
	};

	icssg0: icssg@b000000 {
		compatible = "ti,j721e-icssg";
		reg = <0x00 0xb000000 0x00 0x80000>;
		power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x00 0x0b000000 0x100000>;

		icssg0_mem: memories@0 {
			reg = <0x0 0x2000>,
			      <0x2000 0x2000>,
			      <0x10000 0x10000>;
			reg-names = "dram0", "dram1",
				    "shrdram2";
		};

		icssg0_cfg: cfg@26000 {
			compatible = "ti,pruss-cfg", "syscon";
			reg = <0x26000 0x200>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x26000 0x2000>;

			clocks {
				#address-cells = <1>;
				#size-cells = <0>;

				icssg0_coreclk_mux: coreclk-mux@3c {
					reg = <0x3c>;
					#clock-cells = <0>;
					clocks = <&k3_clks 119 24>, /* icssg0_core_clk */
						 <&k3_clks 119 1>;  /* icssg0_iclk */
					assigned-clocks = <&icssg0_coreclk_mux>;
					assigned-clock-parents = <&k3_clks 119 1>;
				};

				icssg0_iepclk_mux: iepclk-mux@30 {
					reg = <0x30>;
					#clock-cells = <0>;
					clocks = <&k3_clks 119 3>,	/* icssg0_iep_clk */
						 <&icssg0_coreclk_mux>;	/* core_clk */
					assigned-clocks = <&icssg0_iepclk_mux>;
					assigned-clock-parents = <&icssg0_coreclk_mux>;
				};
			};
		};

		icssg0_iep0: iep@2e000 {
			compatible = "ti,am654-icss-iep";
			reg = <0x2e000 0x1000>;
			clocks = <&icssg0_iepclk_mux>;
		};

		icssg0_iep1: iep@2f000 {
			compatible = "ti,am654-icss-iep";
			reg = <0x2f000 0x1000>;
			clocks = <&icssg0_iepclk_mux>;
		};

		icssg0_mii_rt: mii-rt@32000 {
			compatible = "ti,pruss-mii", "syscon";
			reg = <0x32000 0x100>;
		};

		icssg0_mii_g_rt: mii-g-rt@33000 {
			compatible = "ti,pruss-mii-g", "syscon";
			reg = <0x33000 0x1000>;
		};

		icssg0_intc: interrupt-controller@20000 {
			compatible = "ti,icssg-intc";
			reg = <0x20000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "host_intr0", "host_intr1",
					  "host_intr2", "host_intr3",
					  "host_intr4", "host_intr5",
					  "host_intr6", "host_intr7";
		};

		pru0_0: pru@34000 {
			compatible = "ti,j721e-pru";
			reg = <0x34000 0x3000>,
			      <0x22000 0x100>,
			      <0x22400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-pru0_0-fw";
		};

		rtu0_0: rtu@4000 {
			compatible = "ti,j721e-rtu";
			reg = <0x4000 0x2000>,
			      <0x23000 0x100>,
			      <0x23400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-rtu0_0-fw";
		};

		tx_pru0_0: txpru@a000 {
			compatible = "ti,j721e-tx-pru";
			reg = <0xa000 0x1800>,
			      <0x25000 0x100>,
			      <0x25400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-txpru0_0-fw";
		};

		pru0_1: pru@38000 {
			compatible = "ti,j721e-pru";
			reg = <0x38000 0x3000>,
			      <0x24000 0x100>,
			      <0x24400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-pru0_1-fw";
		};

		rtu0_1: rtu@6000 {
			compatible = "ti,j721e-rtu";
			reg = <0x6000 0x2000>,
			      <0x23800 0x100>,
			      <0x23c00 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-rtu0_1-fw";
		};

		tx_pru0_1: txpru@c000 {
			compatible = "ti,j721e-tx-pru";
			reg = <0xc000 0x1800>,
			      <0x25800 0x100>,
			      <0x25c00 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-txpru0_1-fw";
		};

		icssg0_mdio: mdio@32400 {
			compatible = "ti,davinci_mdio";
			reg = <0x32400 0x100>;
			clocks = <&k3_clks 119 1>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <0>;
			bus_freq = <1000000>;
			status = "disabled";
		};
	};

	icssg1: icssg@b100000 {
		compatible = "ti,j721e-icssg";
		reg = <0x00 0xb100000 0x00 0x80000>;
		power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x00 0x0b100000 0x100000>;

		icssg1_mem: memories@b100000 {
			reg = <0x0 0x2000>,
			      <0x2000 0x2000>,
			      <0x10000 0x10000>;
			reg-names = "dram0", "dram1",
				    "shrdram2";
		};

		icssg1_cfg: cfg@26000 {
			compatible = "ti,pruss-cfg", "syscon";
			reg = <0x26000 0x200>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x26000 0x2000>;

			clocks {
				#address-cells = <1>;
				#size-cells = <0>;

				icssg1_coreclk_mux: coreclk-mux@3c {
					reg = <0x3c>;
					#clock-cells = <0>;
					clocks = <&k3_clks 120 54>, /* icssg1_core_clk */
						 <&k3_clks 120 4>;  /* icssg1_iclk */
					assigned-clocks = <&icssg1_coreclk_mux>;
					assigned-clock-parents = <&k3_clks 120 4>;
				};

				icssg1_iepclk_mux: iepclk-mux@30 {
					reg = <0x30>;
					#clock-cells = <0>;
					clocks = <&k3_clks 120 9>,	/* icssg1_iep_clk */
						 <&icssg1_coreclk_mux>;	/* core_clk */
					assigned-clocks = <&icssg1_iepclk_mux>;
					assigned-clock-parents = <&icssg1_coreclk_mux>;
				};
			};
		};

		icssg1_iep0: iep@2e000 {
			compatible = "ti,am654-icss-iep";
			reg = <0x2e000 0x1000>;
			clocks = <&icssg1_iepclk_mux>;
		};

		icssg1_iep1: iep@2f000 {
			compatible = "ti,am654-icss-iep";
			reg = <0x2f000 0x1000>;
			clocks = <&icssg1_iepclk_mux>;
		};

		icssg1_mii_rt: mii-rt@32000 {
			compatible = "ti,pruss-mii", "syscon";
			reg = <0x32000 0x100>;
		};

		icssg1_mii_g_rt: mii-g-rt@33000 {
			compatible = "ti,pruss-mii-g", "syscon";
			reg = <0x33000 0x1000>;
		};

		icssg1_intc: interrupt-controller@20000 {
			compatible = "ti,icssg-intc";
			reg = <0x20000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "host_intr0", "host_intr1",
					  "host_intr2", "host_intr3",
					  "host_intr4", "host_intr5",
					  "host_intr6", "host_intr7";
		};

		pru1_0: pru@34000 {
			compatible = "ti,j721e-pru";
			reg = <0x34000 0x4000>,
			      <0x22000 0x100>,
			      <0x22400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-pru1_0-fw";
		};

		rtu1_0: rtu@4000 {
			compatible = "ti,j721e-rtu";
			reg = <0x4000 0x2000>,
			      <0x23000 0x100>,
			      <0x23400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-rtu1_0-fw";
		};

		tx_pru1_0: txpru@a000 {
			compatible = "ti,j721e-tx-pru";
			reg = <0xa000 0x1800>,
			      <0x25000 0x100>,
			      <0x25400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-txpru1_0-fw";
		};

		pru1_1: pru@38000 {
			compatible = "ti,j721e-pru";
			reg = <0x38000 0x4000>,
			      <0x24000 0x100>,
			      <0x24400 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-pru1_1-fw";
		};

		rtu1_1: rtu@6000 {
			compatible = "ti,j721e-rtu";
			reg = <0x6000 0x2000>,
			      <0x23800 0x100>,
			      <0x23c00 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-rtu1_1-fw";
		};

		tx_pru1_1: txpru@c000 {
			compatible = "ti,j721e-tx-pru";
			reg = <0xc000 0x1800>,
			      <0x25800 0x100>,
			      <0x25c00 0x100>;
			reg-names = "iram", "control", "debug";
			firmware-name = "j7-txpru1_1-fw";
		};

		icssg1_mdio: mdio@32400 {
			compatible = "ti,davinci_mdio";
			reg = <0x32400 0x100>;
			clocks = <&k3_clks 120 4>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <0>;
			bus_freq = <1000000>;
			status = "disabled";
		};
	};

	timesync_router: timesync_router@A40000 {
		compatible = "pinctrl-single";
		reg = <0x0 0xa40000 0x0 0x800>;
		#address-cells = <1>;
		#size-cells = <0>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0x000107ff>;
	};

	gpu: gpu@4e20000000 {
		compatible = "ti,j721e-pvr", "img,pvr-ge8430";
		reg = <0x4e 0x20000000 0x00 0x80000>;
		reg-names = "gpu_regs";
		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>,
				<&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
		power-domain-names = "gpu_0", "gpucore_0";
		clocks = <&k3_clks 125 0>;
		clock-names = "ctrl";
	};

	main_mcan0: can@2701000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02701000 0x00 0x200>,
		      <0x00 0x02708000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 156 1>, <&k3_clks 156 0>;
		clock-names = "cclk", "hclk";
		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
	};

	main_mcan1: can@2711000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02711000 0x00 0x200>,
		      <0x00 0x02718000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 158 1>, <&k3_clks 158 0>;
		clock-names = "cclk", "hclk";
		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
	};

	main_mcan2: can@2721000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02721000 0x00 0x200>,
		      <0x00 0x02728000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 160 1>, <&k3_clks 160 0>;
		clock-names = "cclk", "hclk";
		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
	};

	main_mcan3: can@2731000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02731000 0x00 0x200>,
		      <0x00 0x02738000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 161 1>, <&k3_clks 161 0>;
		clock-names = "cclk", "hclk";
		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
	};

	main_mcan4: can@2741000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02741000 0x00 0x200>,
		      <0x00 0x02748000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 162 1>, <&k3_clks 162 0>;
		clock-names = "cclk", "hclk";
		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
	};

	main_mcan5: can@2751000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02751000 0x00 0x200>,
		      <0x00 0x02758000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 163 1>, <&k3_clks 163 0>;
		clock-names = "cclk", "hclk";
		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
	};

	main_mcan6: can@2761000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02761000 0x00 0x200>,
		      <0x00 0x02768000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 164 1>, <&k3_clks 164 0>;
		clock-names = "cclk", "hclk";
		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
	};

	main_mcan7: can@2771000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02771000 0x00 0x200>,
		      <0x00 0x02778000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 165 1>, <&k3_clks 165 0>;
		clock-names = "cclk", "hclk";
		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
	};

	main_mcan8: can@2781000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02781000 0x00 0x200>,
		      <0x00 0x02788000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 166 1>, <&k3_clks 166 0>;
		clock-names = "cclk", "hclk";
		interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
	};

	main_mcan9: can@2791000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02791000 0x00 0x200>,
		      <0x00 0x02798000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 167 1>, <&k3_clks 167 0>;
		clock-names = "cclk", "hclk";
		interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
	};

	main_mcan10: can@27a1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027a1000 0x00 0x200>,
		      <0x00 0x027a8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 168 1>, <&k3_clks 168 0>;
		clock-names = "cclk", "hclk";
		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
	};

	main_mcan11: can@27b1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027b1000 0x00 0x200>,
		      <0x00 0x027b8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 169 1>, <&k3_clks 169 0>;
		clock-names = "cclk", "hclk";
		interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
	};

	main_mcan12: can@27c1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027c1000 0x00 0x200>,
		      <0x00 0x027c8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 170 1>, <&k3_clks 170 0>;
		clock-names = "cclk", "hclk";
		interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
	};

	main_mcan13: can@27d1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027d1000 0x00 0x200>,
		      <0x00 0x027d8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 171 1>, <&k3_clks 171 0>;
		clock-names = "cclk", "hclk";
		interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
	};

	ti_csi2rx0: ticsi2rx@4500000 {
		compatible = "ti,j721e-csi2rx";
		dmas = <&main_udmap 0x4940>, <&main_udmap 0x4941>, <&main_udmap 0x4942>,
			<&main_udmap 0x4943>, <&main_udmap 0x4944>, <&main_udmap 0x4945>,
			<&main_udmap 0x4946>, <&main_udmap 0x4947>, <&main_udmap 0x4948>,
			<&main_udmap 0x4949>, <&main_udmap 0x494a>, <&main_udmap 0x494b>,
			<&main_udmap 0x494c>, <&main_udmap 0x494d>, <&main_udmap 0x494e>,
			<&main_udmap 0x494f>;
		dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
			    "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", "rx14", "rx15";
		reg = <0x0 0x4500000 0x0 0x1000>;
		power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		cdns_csi2rx0: csi-bridge@4504000 {
			compatible = "cdns,csi2rx";
			reg = <0x0 0x4504000 0x0 0x1000>;
			clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>,
				<&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>;
			clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
				"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
			phys = <&dphy0>;
			phy-names = "dphy";
			power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				csi0_port0: port@0 {
					reg = <0>;
				};

				csi0_port1: port@1 {
					reg = <1>;
				};

				csi0_port2: port@2 {
					reg = <2>;
				};

				csi0_port3: port@3 {
					reg = <3>;
				};

				csi0_port4: port@4 {
					reg = <4>;
				};
			};
		};
	};

	ti_csi2rx1: ticsi2rx@4510000 {
		compatible = "ti,j721e-csi2rx";
		dmas = <&main_udmap 0x4960>, <&main_udmap 0x4961>, <&main_udmap 0x4962>,
			<&main_udmap 0x4963>, <&main_udmap 0x4964>, <&main_udmap 0x4965>,
			<&main_udmap 0x4966>, <&main_udmap 0x4967>, <&main_udmap 0x4968>,
			<&main_udmap 0x4969>, <&main_udmap 0x496a>, <&main_udmap 0x496b>,
			<&main_udmap 0x496c>, <&main_udmap 0x496d>, <&main_udmap 0x496e>,
			<&main_udmap 0x496f>;
		dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
			    "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", "rx14", "rx15";
		reg = <0x0 0x4510000 0x0 0x1000>;
		power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		cdns_csi2rx1: csi-bridge@4514000 {
			compatible = "cdns,csi2rx";
			reg = <0x0 0x4514000 0x0 0x1000>;
			clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>,
				<&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>;
			clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
				"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
			phys = <&dphy1>;
			phy-names = "dphy";
			power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				csi1_port0: port@0 {
					reg = <0>;
				};

				csi1_port1: port@1 {
					reg = <1>;
				};

				csi1_port2: port@2 {
					reg = <2>;
				};

				csi1_port3: port@3 {
					reg = <3>;
				};

				csi1_port4: port@4 {
					reg = <4>;
				};
			};
		};
	};

	dphy0: phy@4580000 {
		compatible = "ti,j721e-dphy", "cdns,dphy";
		reg = <0x0 0x4580000 0x0 0x1100>;
		#phy-cells = <0>;
		power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
	};

	dphy1: phy@4590000 {
		compatible = "ti,j721e-dphy", "cdns,dphy";
		reg = <0x0 0x4590000 0x0 0x1100>;
		#phy-cells = <0>;
		power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
	};
	main_spi3: spi@2130000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x0 0x2130000 0x0 0x400>;
		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 269 1>;
		/* TODO:  */
		power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <1>;
		#size-cells = <0>;
	};
	main_spi5: spi@2150000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x0 0x2150000 0x0 0x400>;
		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 271 1>;
		/* TODO:  */
		power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <1>;
		#size-cells = <0>;
	};
};

而且我的 DTS 文件是

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;

#include "k3-j721e-som-p0.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy-cadence.h>

/ {
	chosen {
		stdout-path = "serial2:115200n8";
		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
	};

	gpio_keys: gpio-keys {
		compatible = "gpio-keys";
		autorepeat;
		pinctrl-names = "default";
		pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default &pps_pins_default &rtk_pins_default &gpio_main_pins_default &gpio_wakeup_pins_default>;

		sw10: sw10 {
			label = "GPIO Key USER1";
			linux,code = <BTN_0>;
			gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>;
		};

		sw11: sw11 {
			label = "GPIO Key USER2";
			linux,code = <BTN_1>;
			gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>;
		};
	};
	xavier-gpio {
		status = "disabled";		
		compatible = "poseidon,xavier-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&xavier_main_pins_default>;
		xavier_power_on = <&main_gpio0 113 GPIO_ACTIVE_HIGH>;
		sw00 {
			/* gpio = <&main_gpio1>; */
			gpio = <&main_gpio1 32 GPIO_ACTIVE_HIGH>;
			gpios = <&main_gpio1 32 GPIO_ACTIVE_HIGH>;
			value = <0>;
		};	//rst->0
		sw01 {
			/* gpio = <&main_gpio0>; */
			gpio = <&main_gpio0 114 GPIO_ACTIVE_HIGH>;
			gpios = <&main_gpio0 114 GPIO_ACTIVE_HIGH>;
			value = <0>;
		};//MODULE_POWER_ON->0
		sw1 {
			gpio = <&main_gpio0 120 GPIO_ACTIVE_HIGH>;
			gpios = <&main_gpio0 120 GPIO_ACTIVE_HIGH>;
			value = <1>;
		};//POWER_BT_N
		
		sw2 {
			/* gpio = <&main_gpio0>; */
			gpio = <&wkup_gpio0 37 GPIO_ACTIVE_LOW>;
			gpios = <&wkup_gpio0 37 GPIO_ACTIVE_LOW>;
			value = <0>;
		};//VSYS_12V_EN
		sw3 {
			/* gpio = <&main_gpio0>; */
			gpio = <&main_gpio0 115 GPIO_ACTIVE_HIGH>;
			gpios = <&main_gpio0 115 GPIO_ACTIVE_HIGH>;
			value = <1>;
		};//VIN_PWR_ON

		sw4 {
			/* gpio = <&main_gpio0>; */
			gpio = <&main_gpio0 114 GPIO_ACTIVE_HIGH>;
			gpios = <&main_gpio0 114 GPIO_ACTIVE_HIGH>;
			value = <1>;
		};//MODULE_POWER_ON
		
		sw5 {
			/* gpio = <&main_gpio1>; */
			gpio = <&main_gpio1 32 GPIO_ACTIVE_HIGH>;
			gpios = <&main_gpio1 32 GPIO_ACTIVE_HIGH>;
			value = <1>;
		};//rst->1
	};
	evm_12v0: fixedregulator-evm12v0 {
		/* main supply */
		compatible = "regulator-fixed";
		regulator-name = "evm_12v0";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_3v3: fixedregulator-vsys3v3 {
		/* Output of LMS140 */
		compatible = "regulator-fixed";
		regulator-name = "vsys_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_5v0: fixedregulator-vsys5v0 {
		/* Output of LM5140 */
		compatible = "regulator-fixed";
		regulator-name = "vsys_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vdd_mmc1: fixedregulator-sd {
		compatible = "regulator-fixed";
		regulator-name = "vdd_mmc1";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		enable-active-high;
		vin-supply = <&vsys_3v3>;
		/* gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; */
	};


	/* ethernet phy mode driver for marvell 1512 */
	phymode {
		status = "disabled";
	};
/*

	sound0: sound@0 {
		compatible = "ti,j721e-cpb-audio";
		model = "j721e-cpb";

		ti,cpb-mcasp = <&mcasp10>;
		ti,cpb-codec = <&pcm3168a_1>;

		clocks = <&k3_clks 184 1>,
			 <&k3_clks 184 2>, <&k3_clks 184 4>,
			 <&k3_clks 157 371>,
			 <&k3_clks 157 400>, <&k3_clks 157 401>;
		clock-names = "cpb-mcasp-auxclk",
			      "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100",
			      "cpb-codec-scki",
			      "cpb-codec-scki-48000", "cpb-codec-scki-44100";
	};
*/

	clk_fusion_25M_fixed: fixed-clock-25M {
				compatible = "fixed-clock";
				#clock-cells = <0>;
				clock-frequency = <25000000>;
			};

			hdmi-connector {
				compatible = "hdmi-connector";
				label = "hdmi";
				type = "a";

				port {
					hdmi_connector_in: endpoint {
						remote-endpoint = <&tfp410_out>;
					};
				};
			};

			dvi-bridge {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "ti,tfp410";

				/* HDMI_PDn */
				pinctrl-names = "default";
				pinctrl-0 = <&dvi_bridge_power_gpio_pins_default>;
				powerdown-gpios = <&main_gpio1 29 GPIO_ACTIVE_HIGH>;

				port@0 {
					reg = <0>;

					tfp410_in: endpoint {
						remote-endpoint = <&dpi_out0>;
						pclk-sample = <1>;
					};
				};

				port@1 {
					reg = <1>;

					tfp410_out: endpoint {
						remote-endpoint =
							<&hdmi_connector_in>;
					};
				};
			};

	pps_gpio: pps-gpio {
		compatible = "pps-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pps_gpio_pin_default>;
		gpios = <&wkup_gpio0 8 GPIO_ACTIVE_HIGH>;
		status = "okay";
	};

	cpsw9g_virt_mac: main_r5fss_cpsw9g_virt_mac0 {
		compatible = "ti,j721e-cpsw-virt-mac";
		dma-coherent;
		ti,psil-base = <0x4a00>;
		ti,remote-name = "mpu_1_0_ethswitch-device-0";

		dmas = <&main_udmap 0xca00>,
		       <&main_udmap 0xca01>,
		       <&main_udmap 0xca02>,
		       <&main_udmap 0xca03>,
		       <&main_udmap 0xca04>,
		       <&main_udmap 0xca05>,
		       <&main_udmap 0xca06>,
		       <&main_udmap 0xca07>,
		       <&main_udmap 0x4a00>;
		dma-names = "tx0", "tx1", "tx2", "tx3",
			    "tx4", "tx5", "tx6", "tx7",
			    "rx";

		virt_emac_port {
			ti,label = "virt-port";
			/* local-mac-address = [0 0 0 0 0 0]; */
		};
	};

	transceiver1: can-phy@0 {
		compatible = "ti,tcan1043";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
		standby-gpios = <&wkup_gpio0 14 GPIO_ACTIVE_LOW>;
		enable-gpios = <&wkup_gpio0 15 GPIO_ACTIVE_HIGH>;
	};
/*
	transceiver2: can-phy@1 {
		compatible = "ti,tcan1042";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
		standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
	};
*/

	wifi_pwr_en: fixedregulator-wifi@0 {
		compatible = "regulator-fixed";
		regulator-name = "wifi_pwr_on";
		pinctrl-names = "default";
		pinctrl-0 = <&wifi_poweron_pins_default>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		regulator-boot-on;
		enable-active-high;
		gpio = <&main_gpio0 41 GPIO_ACTIVE_HIGH>;
	};

	gobinet_pwr_on: fixedregulator-gobinet@0 {
		compatible = "regulator-fixed";
		regulator-name = "gobinet_pwr_on";
		pinctrl-names = "default";
		pinctrl-0 = <&gobinet_poweron_pins_default>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		regulator-boot-on;
		enable-active-high;
		gpio = <&main_gpio0 4 GPIO_ACTIVE_HIGH>;
	};

	gobinet_reset: fixedregulator-gobinet@1 {
		compatible = "regulator-fixed";
		regulator-name = "gobinet_reset";
		pinctrl-names = "default";
		pinctrl-0 = <&gobinet_reset_pins_default>;
		regulator-min-microvolt = <0>;
		regulator-max-microvolt = <0>;
		regulator-always-on;
		regulator-boot-on;
		enable-active-low;
		gpio = <&main_gpio0 5 GPIO_ACTIVE_LOW>;
	};
	gobinet_flymode: fixedregulator-gobinet@2 {
		compatible = "regulator-fixed";
		regulator-name = "gobinet_flymode";
		pinctrl-names = "default";
		pinctrl-0 = <&gobinet_flymode_pins_default>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		regulator-boot-on;
		enable-active-high;
		gpio = <&wkup_gpio0 7 GPIO_ACTIVE_HIGH>;
	};

	gobinet_gnss: fixedregulator-gobinet@2 {
		compatible = "regulator-fixed";
		regulator-name = "gobinet_gnss";
		pinctrl-names = "default";
		pinctrl-0 = <&gobinet_gnss_pins_default>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		regulator-boot-on;
		enable-active-high;
		gpio = <&main_gpio0 53 GPIO_ACTIVE_HIGH>;
	};
	eth_pwr_ctl: fixedregulator-eth@0 {
		compatible = "regulator-fixed";
		regulator-name = "eth_pwr_ctl";
		pinctrl-names = "default";
		pinctrl-0 = <&eth_pwr_pins_default>;
		regulator-min-microvolt = <0>;
		regulator-max-microvolt = <0>;
		regulator-always-on;
		regulator-boot-on;
		enable-active-low;
		gpio = <&main_gpio0 7 GPIO_ACTIVE_LOW>;
	};
	sleep_en: fixedregulator-sleepen@0 {
		compatible = "regulator-fixed";
		regulator-name = "sleepen_ctl";
		pinctrl-names = "default";
		pinctrl-0 = <&sleepen_pins_default>;
		regulator-min-microvolt = <0>;
		regulator-max-microvolt = <0>;
		regulator-always-on;
		regulator-boot-on;
		enable-active-low;
		gpio = <&main_gpio0 6 GPIO_ACTIVE_LOW>;
	};
};

&main_pmx0 {
	sw10_button_pins_default: sw10-button-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */
		>;
	};

	gpio_main_pins_default: gpio-main-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x18c, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */
			J721E_IOPAD(0x1b4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */
		>;
	};

	sja1105_reset_default: sja1105_reset_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x8, PIN_INPUT, 7) /* (AG22) GPIO0_2 */
		>;
	};
	
	spi3_pins_default: spi3_pins_default {
	/* TODO: */
		pinctrl-single,pins = <
			J721E_IOPAD(0x144, PIN_INPUT, 4) /* (Y25) SPI3_CLK */
			J721E_IOPAD(0x11C, PIN_INPUT, 4) /* (AA24) SPI3_CS */
			J721E_IOPAD(0x148, PIN_INPUT, 4) /* (AA26) SPI3_MOSI */
			J721E_IOPAD(0x14C, PIN_INPUT, 4) /* (AA29) SPI3_MISO */
		>;
	};

	pwm4_pins_default: pwm4-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1A0, PIN_OUTPUT, 6) /* (W29) EHRPWM4_A */
			J721E_IOPAD(0x1A4, PIN_OUTPUT, 6) /* (W26) EHRPWM4_B */
		>;
	};

	spi5_pins_default: spi5_pins_default {
	/* TODO: */
		pinctrl-single,pins = <
			J721E_IOPAD(0x1A0, PIN_INPUT, 3) /* (W29) SPI5_CLK */
			J721E_IOPAD(0x19C, PIN_INPUT, 3) /* (W27) SPI5_CS */
			J721E_IOPAD(0x198, PIN_INPUT, 3) /* (V25) SPI5_MOSI */
			J721E_IOPAD(0x1B0, PIN_INPUT, 3) /* (W24) SPI5_MISO */
		>;
	};

	main_mmc1_pins_default: main-mmc1-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
			J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
			J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
			J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
			J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
			J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
			J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
			J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
		>;
	};


    main_mmc2_pins_default: main-mmc2-pins-default {
                pinctrl-single,pins = <
                        J721E_IOPAD(0x274, PIN_INPUT, 0) /* (T25) MMC2_CMD */
                        J721E_IOPAD(0x270, PIN_INPUT, 0) /* (T26) MMC2_CLK */
                        J721E_IOPAD(0x2b0, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
                        J721E_IOPAD(0x26c, PIN_INPUT, 0) /* (T24) MMC2_DAT0 */
                        J721E_IOPAD(0x268, PIN_INPUT, 0) /* (T27) MMC2_DAT1 */
                        J721E_IOPAD(0x264, PIN_INPUT, 0) /* (T29) MMC2_DAT2 */
                        J721E_IOPAD(0x260, PIN_INPUT, 0) /* (T28) MMC2_DAT3 */
                >;
        };

	main_i2c0_pins_default: main-i2c0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
			J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
		>;
	};

	main_i2c1_pins_default: main-i2c1-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
			J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
		>;
	};

	main_i2c3_pins_default: main-i2c3-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x168, PIN_INPUT, 2) /* (V27) RGMII5_TD1.I2C3_SCL */
			J721E_IOPAD(0x16c, PIN_INPUT, 2) /* (U28) RGMII5_TD0.I2C3_SDA */
		>;
	};

	main_uart1_pins_default: main-uart1-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */
			J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */
		>;
	};

	main_uart2_pins_default: main-uart2-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1dc, PIN_INPUT, 3) /* (Y1) SPI1_CLK.UART2_RXD */
			J721E_IOPAD(0x1e0, PIN_OUTPUT, 3) /* (Y5) SPI1_D0.UART2_TXD */
		>;
	};

	main_uart3_pins_default: main-uart3-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0xb8, PIN_INPUT, 8) /* (AE27) PRG0_PRU0_GPO2.UART3_RXD */
			J721E_IOPAD(0xbc, PIN_OUTPUT, 8) /* (AD26) PRG0_PRU0_GPO3.UART3_TXD */
		>;
	};

	main_uart4_pins_default: main-uart4-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1a8, PIN_INPUT, 1) /* (Y29) RGMII6_RD3.UART4_CTSn */
			J721E_IOPAD(0x1ac, PIN_OUTPUT, 1) /* (Y27) RGMII6_RD2.UART4_RTSn */
			J721E_IOPAD(0x190, PIN_INPUT, 1) /* (W23) RGMII6_TD3.UART4_RXD */
			J721E_IOPAD(0x194, PIN_OUTPUT, 1) /* (W28) RGMII6_TD2.UART4_TXD */
		>;
	};

	main_uart5_pins_default: main-uart5-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1d4, PIN_INPUT, 3) /* (Y3) SPI1_CS0.UART5_RXD */
			J721E_IOPAD(0x1d8, PIN_OUTPUT, 3) /* (W4) SPI1_CS1.UART5_TXD */
		>;
	};

	main_uart8_pins_default: main-uart8-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x124, PIN_INPUT, 14) /* (Y24) PRG0_PRU1_GPO9.UART8_RXD */
			J721E_IOPAD(0x128, PIN_OUTPUT, 14) /* (AA25) PRG0_PRU1_GPO10.UART8_TXD */
		>;
	};

	main_uart0_pins_default: main-uart0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
			J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
		>;
	};
	
	mcan0_pins_default: mcan0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */
			J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */
		>;
	};

	mcan1_pins_default: mcan1-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x210, PIN_INPUT, 0) /* (W3) MCAN1_RX */
			J721E_IOPAD(0x214, PIN_OUTPUT, 0) /* (V4) MCAN1_TX */
		>;
	};

	mcan2_pins_default: mcan2-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1f0, PIN_INPUT, 3) /* (AC2) UART0_CTSn.MCAN2_RX */
			J721E_IOPAD(0x1f4, PIN_OUTPUT, 3) /* (AB1) UART0_RTSn.MCAN2_TX */
		>;
	};

	mcan3_pins_default: mcan3-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x200, PIN_INPUT, 1) /* (AC4) UART1_CTSn.MCAN3_RX */
			J721E_IOPAD(0x204, PIN_OUTPUT, 1) /* (AD5) UART1_RTSn.MCAN3_TX */
		>;
	};

	mcan5_pins_default: mcan5-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x50, PIN_INPUT, 6) /* (AE21) PRG1_PRU0_GPO18.MCAN5_RX */
			J721E_IOPAD(0x4c, PIN_OUTPUT, 6) /* (AJ21) PRG1_PRU0_GPO17.MCAN5_TX */
		>;
	};

	mcan9_pins_default: mcan9-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0xd0, PIN_INPUT, 6) /* (AC27) PRG0_PRU0_GPO8.MCAN9_RX */
			J721E_IOPAD(0xcc, PIN_OUTPUT, 6) /* (AC28) PRG0_PRU0_GPO7.MCAN9_TX */
		>;
	};

	mcan10_pins_default: mcan10-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0xd8, PIN_INPUT, 6) /* (AB25) PRG0_PRU0_GPO10.MCAN10_RX */
			J721E_IOPAD(0xd4, PIN_OUTPUT, 6) /* (AB26) PRG0_PRU0_GPO9.MCAN10_TX */
		>;
	};

	mcan13_pins_default: mcan13-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x154, PIN_INPUT, 6) /* (AA27) PRG0_MDIO0_MDC.MCAN13_RX */
			J721E_IOPAD(0x150, PIN_OUTPUT, 6) /* (Y26) PRG0_MDIO0_MDIO.MCAN13_TX */
		>;
	};

	deser0_power_gpio_pins_default: deser0-gpio-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x120, PIN_OUTPUT, 7) /* (AA28) GPIO0_71 */
			J721E_IOPAD(0x230, PIN_OUTPUT, 1) /* (U2) GPIO1_11 */
			J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) GPIO0_97 */
		>;
	};

	deser1_power_gpio_pins_default: deser1-gpio-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x0F0, PIN_OUTPUT, 7) /* (AH28) GPIO0_59 */
			J721E_IOPAD(0x234, PIN_OUTPUT, 1) /* (U3) GPIO1_12 */
		>;
	};

	cam_a_power_en_pins_default: cam-a-pwren-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0xB0, PIN_OUTPUT, 7) /* (AF28) GPIO0_43 */
		>;
	};

	cam_b_power_en_pins_default: cam-b-pwren-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0xDC, PIN_OUTPUT, 7) /* (AJ28) GPIO0_54 */
		>;
	};

	dvi_bridge_power_gpio_pins_default: dvi-bridge-gpio-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x290, PIN_OUTPUT, 7) /* (U6) USB0_DRVVBUS GPIO1_29 */
		>;
	};

	dss_vout0_pins_default: dss-vout0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */
			J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */
			J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */
			J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */
			J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */
			J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */
			J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */
			J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */
			J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */
			J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */
			J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */
			J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */
			J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */
			J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */
			J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */
			J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */
			J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */
			J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */
			J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */
			J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */
			J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */
			J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */
			J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */
			J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */
			J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */
			J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */
			J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */
			J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */
		>;
	};
	xavier_main_pins_default: xavier-main-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1c8, PIN_INPUT, 7) /* (AA1) SPI0_CLK.GPIO0_113 */
			J721E_IOPAD(0x1cc, PIN_OUTPUT, 7) /* (AB5) SPI0_D0.GPIO0_114 */
			J721E_IOPAD(0x1d0, PIN_OUTPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */
			J721E_IOPAD(0x1e4, PIN_OUTPUT, 7) /* (Y2) SPI1_D1.GPIO0_120 */
			J721E_IOPAD(0x29c, PIN_OUTPUT, 7) /* (AC3) MLB0_MLBDP.GPIO1_32 */
		>;
	};
	gobinet_poweron_pins_default: gobinet-poweron-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x10, PIN_OUTPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */
		>;
	};
	gobinet_reset_pins_default: gobinet-reset-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x14, PIN_OUTPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */
		>;
	};
	gobinet_gnss_pins_default: gobinet-gnss-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1c0, PIN_OUTPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */
		>;
	};
	eth_pwr_pins_default: eth-pwr-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1c, PIN_OUTPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */
		>;
	};
	sleepen_pins_default: sleepen-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x18, PIN_OUTPUT, 7) /* (AD20) PRG1_PRU0_GPO5.GPIO0_6 */
		>;
	};
	sja1124_pins_default: sja1124-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x20, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */
			J721E_IOPAD(0x2c, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */
			J721E_IOPAD(0x54, PIN_INPUT, 7) /* (AH21) PRG1_PRU0_GPO19.GPIO0_20 */
		>;
	};
	wifi_poweron_pins_default: wifi-poweron-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0xa8, PIN_OUTPUT, 7) /* (AD19) PRG1_MDIO0_MDIO.GPIO0_41 */
		>;
	};
	rtk_pins_default: rtk-pins-default {
			pinctrl-single,pins = <
			J721E_IOPAD(0x1c4, PIN_OUTPUT, 7) /* (Y4) SPI0_CS1.GPIO0_112 */
		>;	
	};
};

&wkup_pmx0 {
	sw11_button_pins_default: sw11-button-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
		>;
	};

	gpio_wakeup_pins_default: gpio-wakeup-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xc8, PIN_INPUT, 7) /* (F29) WKUP_GPIO0_6 */
			J721E_WKUP_IOPAD(0x54, PIN_INPUT, 7) /* (E22) MCU_OSPI1_CSn1.WKUP_GPIO0_37 */
		>;
	};

	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
			J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
			J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
			J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
			J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
			J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
			J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
			J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
			J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
			J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
			J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
			J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
			/* J721E_WKUP_IOPAD(0x00cc, PIN_INPUT, 2) (G28) MCU_CPTS0_HW2TSPUSH */
		>;
	};

	mcu_mdio_pins_default: mcu-mdio1-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */
			J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */
		>;
	};

	pps_pins_default: pps-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 7) /* (F22) MCU_OSPI1_CLK.WKUP_GPIO0_29 */
			J721E_WKUP_IOPAD(0x38, PIN_INPUT, 7) /* (A23) MCU_OSPI1_LBCLKO.WKUP_GPIO0_30 */
			J721E_WKUP_IOPAD(0x3c, PIN_OUTPUT, 7) /* (B23) MCU_OSPI1_DQS.WKUP_GPIO0_31 */
			J721E_WKUP_IOPAD(0x40, PIN_OUTPUT, 7) /* (D22) MCU_OSPI1_D0.WKUP_GPIO0_32 */
			J721E_WKUP_IOPAD(0x44, PIN_INPUT, 7) /* (G22) MCU_OSPI1_D1.WKUP_GPIO0_33 */
			J721E_WKUP_IOPAD(0x48, PIN_INPUT, 7) /* (D23) MCU_OSPI1_D2.WKUP_GPIO0_34 */
			J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 7) /* (C23) MCU_OSPI1_D3.WKUP_GPIO0_35 */
			J721E_WKUP_IOPAD(0x50, PIN_INPUT, 7) /* (C22) MCU_OSPI1_CSn0.WKUP_GPIO0_36 */
		>;
	};

	mcu_mcan0_pins_default: mcu-mcan0-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */
			J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */
		>;
	};
	mcu_mcan1_pins_default: mcu-mcan1-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */
			J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */
		>;
	};

	mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */
			J721E_WKUP_IOPAD(0xe8, PIN_OUTPUT, 7) /* (H29) WKUP_GPIO0_14 */
			J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 7) /* (J27) WKUP_GPIO0_15 */
		>;
	};

	vdd_mmc1_en_pins_default: vdd-mmc1-en-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */
		>;
	};
	wkup_uart0_pins_default: wkup-uart0-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
			J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
		>;
	};
	gobinet_flymode_pins_default: gobinet-flymode-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xcc, PIN_OUTPUT, 7) /* (G28) WKUP_GPIO0_7 */
		>;
	};
	mcu_spi0_pins_default: mcu-spi0-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x90, PIN_OUTPUT, 0) /* (E27) MCU_SPI0_CLK */
			J721E_WKUP_IOPAD(0x94, PIN_OUTPUT, 0) /* (E24) MCU_SPI0_D0 */
			J721E_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (E28) MCU_SPI0_D1 */
			J721E_WKUP_IOPAD(0x9c, PIN_OUTPUT, 0) /* (E25) MCU_SPI0_CS0 */
		>;
	};

	pps_gpio_pin_default: pps-gpio-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_8 */
		>;
	};

	mcu_adc0_pins_default: mcu-adc0-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x130, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN0 */
			J721E_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (K26) MCU_ADC0_AIN1 */
			J721E_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (K28) MCU_ADC0_AIN2 */
			J721E_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (L28) MCU_ADC0_AIN3 */
			J721E_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN4 */
		>;
	};

	deser1_int_pins_default: deser1-int-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x30, PIN_INPUT, 7) /* (E19) GPIO0_28 */
		>;
	};

};

&mcu_uart0 {
	status = "disabled";
};

&wkup_uart0 {
	/* Wakeup UART is used by System firmware */
	/* status = "reserved"; */
	pinctrl-names = "default";
	pinctrl-0 = <&wkup_uart0_pins_default>;
	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;	
};

&main_uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart0_pins_default>;
	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};

&main_uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart1_pins_default>;
	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};

&main_uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart2_pins_default>;
	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};

&main_uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart3_pins_default>;
	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};

&main_uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart4_pins_default>;
	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};

&main_uart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart5_pins_default>;
	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};

&main_uart6 {
	status = "disabled";
};

&main_uart7 {
	/* UART not brought out */
	status = "disabled";
};

&main_uart8 {
	/* UART not brought out */
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart8_pins_default>;
	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};

&main_uart9 {
	/* UART not brought out */
	status = "disabled";
};

&main_gpio2 {
	status = "disabled";
};

&main_gpio3 {
	status = "disabled";
};

&main_gpio4 {
	status = "disabled";
};

&main_gpio5 {
	status = "disabled";
};

&main_gpio6 {
	status = "disabled";
};

&main_gpio7 {
	status = "disabled";
};

&wkup_gpio1 {
	status = "disabled";
};

&main_sdhci0 {
	/* eMMC */
	non-removable;
	ti,driver-strength-ohm = <50>;
	disable-wp;
};

&main_sdhci1 {
	/* SD/MMC */
/* ////////////////////lyl/////////// */
	no-1-8-v;
	cap-mmc-hw-reset = <0>;
	full-pwr-cycle = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&main_mmc1_pins_default>;
	ti,driver-strength-ohm = <50>;
	disable-wp;
};

&main_sdhci2 {
	/* Unused */
	non-removable;
	cap-mmc-hw-reset = <0>;
	full-pwr-cycle = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&main_mmc2_pins_default>;
	ti,driver-strength-ohm = <50>;
	disable-wp;
	ti,fails-without-test-cd = <1>;
};

&usb_serdes_mux {
	idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
};

&serdes_ln_ctrl {
        idle-states = <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
		      <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>,
		      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
		      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
		      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
};

&serdes_wiz3 {
	typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
	typec-dir-debounce-ms = <700>;	/* TUSB321, tCCB_DEFAULT 133 ms */
};

&serdes3 {
	serdes3_usb_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_USB3>;
		resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
	};
};

&usbss0 {
	pinctrl-names = "default";
	/* pinctrl-0 = <&main_usbss0_pins_default>; */
	ti,vbus-divider;
};

&usb0 {
	dr_mode = "otg";
	maximum-speed = "super-speed";
	phys = <&serdes3_usb_link>;
	phy-names = "cdns3,usb3-phy";
};

&serdes2 {
	serdes2_usb_link: phy@1 {
		reg = <1>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_USB3>;
		resets = <&serdes_wiz2 2>;
	};
};
&usbss1 {
	pinctrl-names = "default";
	ti,vbus-divider;
};

&usb1 {
	dr_mode = "host";
	maximum-speed = "super-speed";
	phys = <&serdes2_usb_link>;
	phy-names = "cdns3,usb3-phy";
};

&ospi1 {
	status = "disabled";
};

&tscadc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_adc0_pins_default>; 
	adc {
		ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
};

&tscadc1 {
	status = "disabled";
};

&main_i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c0_pins_default>;
	clock-frequency = <400000>;
};

&main_i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c1_pins_default>;
	clock-frequency = <400000>;
	#address-cells = <1>;
	#size-cells = <0>;

	/* Poseidon V2.5 */
	regulator@28 {
		compatible = "maxim,max20087";
		reg = <0x28>;
		in-supply = <&evm_12v0>;
		vdd-supply = <&vsys_3v3>;

		pinctrl-names = "default";
		pinctrl-0 = <&cam_a_power_en_pins_default>;
		enable-gpios = <&main_gpio0 43 GPIO_ACTIVE_HIGH>;

		regulators {
			OUT1 {
				regulator-name = "CAM_VOUT4";
				regulator-always-on;
			};
			OUT2 {
				regulator-name = "CAM_VOUT1";
				regulator-always-on;
			};
			OUT3 {
				regulator-name = "CAM_VOUT3";
				regulator-always-on;
			};
			OUT4 {
				regulator-name = "CAM_VOUT2";
				regulator-always-on;
			};
		};
	};

	regulator@29 {
		compatible = "maxim,max20087";
		reg = <0x29>;
		in-supply = <&evm_12v0>;
		vdd-supply = <&vsys_3v3>;

		pinctrl-names = "default";
		pinctrl-0 = <&cam_b_power_en_pins_default >;
		enable-gpios = <&main_gpio0 54 GPIO_ACTIVE_HIGH>;

		regulators {
			OUT1 {
				regulator-name = "CAM_VOUT8";
				regulator-always-on;
			};
			OUT2 {
				regulator-name = "CAM_VOUT5";
				regulator-always-on;
			};
			OUT3 {
				regulator-name = "CAM_VOUT7";
				regulator-always-on;
			};
			OUT4 {
				regulator-name = "CAM_VOUT6";
				regulator-always-on;
			};
		};
	};

	gmsl-deser@69 {
		compatible = "maxim,max96712";

		reg-names = "main", "ser0", "ser1", "ser2", "ser3";
		reg       = <0x69>, <0x41>, <0x42>, <0x43>, <0x44>;

		clocks = <&clk_fusion_25M_fixed>;

		i2c-alias-pool = /bits/ 16 <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>;

		data-rate = <1500000000>;

		pinctrl-names = "default";
		pinctrl-0 = <&deser0_power_gpio_pins_default>;
		powerdown-gpios = <&main_gpio0 71 GPIO_ACTIVE_HIGH>;
		int-gpios = <&main_gpio0 97 GPIO_ACTIVE_HIGH>;

		max96712_0_ports: ports {
			#address-cells = <1>;
			#size-cells = <0>;

			/* CSI-2 */
			port@4 {
				reg = <4>;
				max96712_0_csi_out: endpoint {
					clock-lanes = <0>;
					data-lanes = <1 2 3 4>;
					remote-endpoint = <&csi2rx0_in_sensor>;
				};
			};
		};

		max96712_0_atr: i2c-atr {
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

	gmsl-deser@6b {
		compatible = "maxim,max96712";

		reg-names = "main", "ser0", "ser1", "ser2", "ser3";
		reg       = <0x6b>, <0x45>, <0x46>, <0x47>, <0x48>;

		clocks = <&clk_fusion_25M_fixed>;

		i2c-alias-pool = /bits/ 16 <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>;

		data-rate = <1500000000>;

		pinctrl-names = "default";
		pinctrl-0 = <&deser1_power_gpio_pins_default &deser1_int_pins_default>;
		powerdown-gpios = <&main_gpio0 59 GPIO_ACTIVE_HIGH>;
		int-gpios = <&wkup_gpio0 28 GPIO_ACTIVE_HIGH>;

		max96712_1_ports: ports {
			#address-cells = <1>;
			#size-cells = <0>;

			/* CSI-2 */
			port@4 {
				reg = <4>;
				max96712_1_csi_out: endpoint {
					clock-lanes = <0>;
					data-lanes = <1 2 3 4>;
					remote-endpoint = <&csi2rx1_in_sensor>;
				};
			};
		};

		max96712_1_atr: i2c-atr {
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

};

&main_i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c3_pins_default>;
	clock-frequency = <400000>;
};



&mcu_cpsw {
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;

};

&davinci_mdio {
	phy2: ethernet-phy@2 {
		reg = <0x2>;
		reset-gpios = <&main_gpio0 44 GPIO_ACTIVE_LOW>;
	};
	phy3: ethernet-phy@3 {
		reg = <0x3>;
		reset-gpios = <&main_gpio0 47 GPIO_ACTIVE_LOW>;
	};
	phy4: ethernet-phy@4 {
		reg = <0x4>;
		reset-gpios = <&main_gpio0 49 GPIO_ACTIVE_LOW>;
	};
};

&cpsw_port1 {
	phy-mode = "rgmii-id";
	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};



&mcasp0 {
	status = "disabled";
};

&mcasp1 {
	status = "disabled";
};

&mcasp2 {
	status = "disabled";
};

&mcasp3 {
	status = "disabled";
};

&mcasp4 {
	status = "disabled";
};

&mcasp5 {
	status = "disabled";
};

&mcasp6 {
	status = "disabled";
};

&mcasp7 {
	status = "disabled";
};

&mcasp8 {
	status = "disabled";
};

&mcasp9 {
	status = "disabled";
};

&mcasp10 {
	status = "disabled";
};

&mcasp11 {
	status = "disabled";
};

&cmn_refclk1 {
	clock-frequency = <100000000>;
};

&wiz0_pll1_refclk {
	assigned-clocks = <&wiz0_pll1_refclk>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz0_refclk_dig {
	assigned-clocks = <&wiz0_refclk_dig>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz1_pll1_refclk {
	assigned-clocks = <&wiz1_pll1_refclk>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz1_refclk_dig {
	assigned-clocks = <&wiz1_refclk_dig>;
	assigned-clock-parents = <&cmn_refclk1>;
};

/* add by huangl1383. disable the serdes0 and pcie. */
&serdes_wiz0 {
	status = "disabled";
};
&serdes0 {
	status = "disabled";
	assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
	assigned-clock-parents = <&wiz0_pll1_refclk>;
};

&serdes1 {
	assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
	assigned-clock-parents = <&wiz1_pll1_refclk>;

	serdes1_pcie_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
	};
};

&pcie1_rc {
//	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
	phys = <&serdes1_pcie_link>;
	phy-names = "pcie-phy";
	num-lanes = <2>;
};

&pcie2_rc {
	/* Unused */
	status = "disabled";
};

&pcie1_ep {
	phys = <&serdes1_pcie_link>;
	phy-names = "pcie-phy";
	num-lanes = <2>;
	status = "disabled";
};

&pcie2_ep {
	status = "disabled";
};

&pcie3_rc {
	status = "disabled";
};

&pcie3_ep {
	status = "disabled";
};

&mcu_mcan0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_mcan0_pins_default>;
	phys = <&transceiver1>;
};

&mcu_mcan1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_mcan1_pins_default>;
};

&main_mcan0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcan0_pins_default>;
};

&main_mcan1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcan1_pins_default>;
};

&main_mcan2 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcan2_pins_default>;
};

&main_mcan3 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcan3_pins_default>;
};

&main_mcan4 {
	status = "disabled";
};

&main_mcan5 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcan5_pins_default>;
};

&main_mcan6 {
	status = "disabled";
};

&main_mcan7 {
	status = "disabled";
};

&main_mcan8 {
	status = "disabled";
};

&main_mcan9 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcan9_pins_default>;
};

&main_mcan10 {
	status = "disabled";
};

&main_mcan11 {
	status = "disabled";
};

&main_mcan12 {
	status = "disabled";
};

&main_mcan13 {
	status = "disabled";
};


&csi0_port0 {
	status = "okay";
	csi2rx0_in_sensor: endpoint {
		remote-endpoint = <&max96712_0_csi_out>;
		bus-type = <4>; /* CSI2 DPHY. */
		clock-lanes = <0>;
		data-lanes = <1 2 3 4>;
    };
};

&csi1_port0 {
	status = "okay";

	csi2rx1_in_sensor: endpoint {
		remote-endpoint = <&max96712_1_csi_out>;
		bus-type = <4>; /* CSI2 DPHY. */
		clock-lanes = <0>;
		data-lanes = <1 2 3 4>;
	};
};

&csi0_port1 {
	status = "disabled";
};

&csi0_port2 {
	status = "disabled";
};

&csi0_port3 {
	status = "disabled";
};

&csi0_port4 {
	status = "disabled";
};

&dss {
	pinctrl-names = "default";
	pinctrl-0 = <&dss_vout0_pins_default>;
	/*
	 * These clock assignments are chosen to enable the following outputs:
	 *
	 * VP0 - DisplayPort SST
	 * VP1 - DPI0
	 * VP2 - DSI
	 * VP3 - DPI1
	 */

	assigned-clocks = <&k3_clks 152 1>,
			  <&k3_clks 152 4>,
			  <&k3_clks 152 9>,
			  <&k3_clks 152 13>;
	assigned-clock-parents = <&k3_clks 152 2>,	/* PLL16_HSDIV0 */
				 <&k3_clks 152 6>,	/* PLL19_HSDIV0 */
				 <&k3_clks 152 11>,	/* PLL18_HSDIV0 */
				 <&k3_clks 152 18>;	/* PLL23_HSDIV0 */
};

&dss_ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@1 {
		reg = <1>;

		dpi_out0: endpoint {
			remote-endpoint = <&tfp410_in>;
		};
	};
};

&ehrpwm4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm4_pins_default>;
	status = "okay";
};

&main_spi3 {
    pinctrl-names = "default";
    pinctrl-0 = <&spi3_pins_default &sja1105_reset_default>;
	ti,pindir-d0-out-d1-in = <1>;
	status = "okay";


	/* ADG704BRMZ 1:4 SPI mux/demux */
	sja1105: ethernet-switch@0 {
		reg = <0x0>;
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "nxp,sja1105q";
		/* 12 MHz */
		spi-max-frequency = <12000000>;
		/* Sample data on trailing clock edge */
		spi-cpha;
		/* SPI controller settings for SJA1105 timing requirements */
		fsl,spi-cs-sck-delay = <1000>;
		fsl,spi-sck-cs-delay = <1000>;
		reset-gpios = <&main_gpio0 2 GPIO_ACTIVE_LOW>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				/* RGMII5" */
				ethernet = <&mcu_cpsw>;
				phy-mode = "rgmii-id";
				label = "swp0";
				reg = <0>;
				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};
			port@1 {
				/* PEB RGMII0(EXP board). */
				phy-mode = "rgmii-id";
				label = "swp1";
				reg = <1>;
				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};
			port@2 {
				/* PEB RGMII1(EXP board). */
				phy-mode = "rgmii-id";
				label = "swp2";
				reg = <2>;
				sja1105,role-mac = <1>;
				phy-handle = <&phy2>;
			};
			port@3 {
				/* to SW_PHY3 */
				label = "swp3";
				phy-mode = "rgmii-id";
				reg = <3>;
				sja1105,role-mac = <1>;
				phy-handle = <&phy3>;
			};
			port@4 {
				/* to SW_PHY4 */
				label = "swp4";
				phy-mode = "rgmii-id";
				reg = <4>;
				sja1105,role-mac = <1>;
				phy-handle = <&phy4>;
			};
		};
	};
};

&main_spi5 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi5_pins_default>;
	status="okay";
	//ti,pindir-d0-out-d1-in;
	spidev@0 {
		spi-max-frequency = <24000000>;
		reg = <0>;
		compatible = "linux,spidev";
	};
};

&ufs_wrapper  {
	status = "disabled";
};

&mcu_spi0 {
    pinctrl-names = "default";
    pinctrl-0 = <&mcu_spi0_pins_default &sja1124_pins_default>;
	ti,pindir-d0-out-d1-in = <1>;
	status = "okay";
	sja1124: spi-lin@0 {
		reg = <0x0>;
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "nxp,sja1124";
		/* 12 MHz */
		spi-max-frequency = <2000000>;
		/* Sample data on trailing clock edge */
		spi-cpha;
		int-gpio = <&main_gpio0 20 GPIO_ACTIVE_LOW>;
		channels = <1 1 0 0>;
		pll_mul = <5>;/* multiplication factor = 15. */
		/* baudrate = PLLCLK / (16 * IBR + FBR). */
		fbrs = <11 11 0 0>;/* */
		ibrs = <97 97 0 0>;
	};

};

#define TS_OFFSET(pa, val)     (0x4+(pa)*4) (0x10000 | val)

&timesync_router {
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_cpts>;
	status = "okay";

	/* timesync routing */
	mcu_cpts: mcu_cpts {
			pinctrl-single,pins = <
				/* pps [cpts genf0] in16 -> out34 [cpts SYNC0_OUT] */
				TS_OFFSET(34, 16)    /* cpts SYNC0_OUT  */
				/* pps [cpts genf1] in17 -> out35 [cpts SYNC1_OUT] */
				TS_OFFSET(35, 17)    /* cpts SYNC1_OUT  */
			>;
	};
};

My base SDK 为8.0、而不是8.2。