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您好、TI！
我想将 Keystone 2 66AK2H12/66AK2H14评估板上的 ARM CPU 频率从1.4GHz 更改为较低的值。 我该如何处理它？
我目前正在运行 VxWorks。 我认为降低 CPU 频率可以从电路板 uBoot 提示符(而不是从 VxWorks 引导提示符)实现、但反复多次尝试不断点击"ESC"
键在电路板上电期间、我无法在 uBoot 提示符处停止。 还有其他改变 ARM 频率的方法吗？ 或者、如果是 uBoot、进入提示状态的键序列是什么？
请建议：
谢谢！
杰瑞
Jerry、
有关更改 ARM 频率的信息、请参阅此 E2E 主题。
要在 u-boot 提示符下停止、 "按任意键停止自动引导："(2到3秒内)
请参考此常见问题解答中的最后一个屏幕截图：[FAQ] 66AK2E05：如何将 u-boot 刷写到 K2E 的 SPI 中？？ 使用 PROCESSOR-SDK-LINUX-K2E -处理器论坛-处理器- TI E2E 支持论坛
此致
尚卡里
杰瑞
我在下面附上了 pdf。 转至" 如何更改 Tetris 和 Core PLL 速度"部分并进行检查。
e2e.ti.com/.../4401.MCSDK-UG-Chapter-Exploring-_2D00_-Texas-Instruments-Wiki.pdf
此致
尚卡里
尊敬的 Shankari：
非常感谢您的答复。
我认为我需要解决的第一个问题是进入 U-boot 提示符。 当前没有 U-boot 自动引导倒计时、当电路板上电时、它直接从 U-boot 跳到 VxWorks 引导。 在显示 U-boot 信息和 VxWorks boot 的屏幕之间"点击"任何键都不会中断跳转(在屏幕显示 U-boot 信息之前、也不会继续"点击"键)。 您有什么建议如何停止跳转至 VxWorks 启动？
此致
杰瑞
尊敬的 Shankari：
不可以、VxWorks 不是 TI 软件包的一部分。 从不同的角度来看、是否有其他方法可以修改内核 PLL 速度、或许可以通过直接寄存器配置而不是 U-boot？ 观察 66AK2Hxx 多核 DSP+ARM
KeyStone II 片上系统(SoC)(SPRS866G–2012年11月–2017年10月修订)表11-28、ARM 频率是否会通过直接在寄存器中设置 PLLD、PLLM 和 BOOTMODE 值来更改？
此致
杰瑞
Jerry、
是的、可通过寄存器设置实现。
它在 K2H GEL 文件中给出：-e2e.ti.com/.../7180.xtcievmk2x_5F00_arm.gel
--
ARM PLL @器
* 100MHz 至1.0GHz 工作频率
* 100MHz 至1.4GHz 工作频率
* 175MHz 至1.4GHz 工作频率
--
//设置主 PLL 索引= 3 -> 122.88MHz 至983.04MHz 操作
SET_Pll1 (3)；
//设置 ARM PLL 索引= 1 -> 125MHz 至1000MHz 运行
SET_Tetris_PLL (1)；
--
if (index => 1)｛// 125MHz -> 1.0GHz
CLKIN_val = 125；//将 CLKIN 设置为125MHz
pllm_val = 16；//将 PLLM (PLL 倍频器)设置为 x20
OD_val = 2；//将 OD 设置为固定的/2
｝
否则、if (index == 2)｛// 125MHz -> 1.4GHz
CLKIN_val = 125；//将 CLKIN 设置为125MHz
pllm_val = 22；//设置 PLLM (PLL 乘法器)至 x28
OD_val = 2；//将 OD 设置为固定的/2
｝
否则、if (index == 3)｛// 174.825MHz -> 1.4GHz
CLKIN_val = 174.825；//将 CLKIN 设置为174.825MHz
PLLM_val = 16；//将 PLLM (PLL 倍频器)设置为 x16
OD_val = 2；//将 OD 设置为固定的/2
｝
//********************************************************************************************************************************
//********************************************************************************************************************************
/*
Set_Pll1() - This function executes the main PLL initialization
sequence needed to get the main PLL up after coming out of an initial power up
before it is locked or after it is already locked.
Index value determines multiplier, divier used and clock reference assumed for
output display.
*/
Set_Pll1(int index)
{
int i, TEMP;
unsigned int BYPASS_val;
unsigned int BWADJ_val;
unsigned int OD_val;
float CLKIN_val;
unsigned int PLLM_val;
unsigned int PLLD_val;
unsigned int PLLDIV3_val; //example value for SYSCLK2 (from 6614 spec) Default /2 - Fast Peripherals, (L2, MSMC, DDR3 EMIF, EDMA0...)
unsigned int PLLDIV4_val; //example value for SYSCLK3 (from 6614 spec) Default /3 - Switch Fabric
unsigned int PLLDIV7_val; //example value for SYSCLK6 (from 6614 spec) Defualt /6 - Slow Peripherals (UART, SPI, I2C, GPIO...)
unsigned int debug_info_on;
unsigned int delay;
if(index == 1){ // 122.88 MHz -> 614.4 MHz
CLKIN_val = 122.88; // setup CLKIN to 122.88 MHz
PLLM_val = 10; // setup PLLM (PLL multiplier) to x10
PLLD_val = 1; // setup PLLD (reference divider) to /1
OD_val = 2; // setup OD to a fixed /2
}
else if(index == 2){ // 122.88MHz -> 737.28 MHz
CLKIN_val = 122.88; // setup CLKIN to 122.88 MHz
PLLM_val = 12; // setup PLLM (PLL multiplier) to x12
PLLD_val = 1; // setup PLLD (reference divider) to /1
OD_val = 2; // setup OD to a fixed /2
}
else if(index == 3){ // 122.88MHz -> 983.04 MHz
CLKIN_val = 122.88; // setup CLKIN to 122.88 MHz
PLLM_val = 16; // setup PLLM (PLL multiplier) to x12
PLLD_val = 1; // setup PLLD (reference divider) to /1
OD_val = 2; // setup OD to a fixed /2
}
else if(index == 4){ // 122.88 MHz -> 1.2 GHz
CLKIN_val = 122.88; // setup CLKIN to 122.88 MHz
PLLM_val = 625; // setup PLLM (PLL multiplier) to x625
PLLD_val = 32; // setup PLLD (reference divider) to /32
OD_val = 2; // setup OD to a fixed /2
}
else if(index == 5){ // 122.88 MHz -> 1.228 GHz
CLKIN_val = 122.88; // setup CLKIN to 122.88 MHz
PLLM_val = 20; // setup PLLM (PLL multiplier) to x20
PLLD_val = 1; // setup PLLD (reference divider) to /1
OD_val = 2; // setup OD to a fixed /2
}
PLLDIV3_val = 3; // setup PLL output divider 3 to /3
PLLDIV4_val = 5; // setup PLL output divider 4 to /3
PLLDIV7_val = 6; // setup PLL output divider 7 to /6
BYPASS_val = PLL1_SECCTL & ~BYPASS_MASK; // get value of the BYPASS field
BWADJ_val = (PLLM_val) >> 1; // setup BWADJ to be 1/2 the value of PLLM
OD_val = 2; // setup OD to a fixed /2
debug_info_on = 1;
delay = 1000; // fix this!
/* Step 1: Unlock Boot Config Registers */
KICK0 = KICK0_UNLOCK;
KICK1 = KICK1_UNLOCK;
/* Step 2: Check if SECCTL bypass is low or high indicating what state the Main PLL is currently in. if
the Main PLL is in bypass still (not yet setup) execute the following steps. */
if(BYPASS_val != 0x00000000){ // PLL bypass enabled - Execute PLL setup for PLL fresh out of power on reset
if(debug_info_on){
GEL_TextOut("Detected PLL bypass enabled: SECCTL[BYPASS] = %x\n",,,,, BYPASS_val);
}
/* Step 2a: Set MAINPLLCTL1[ENSAT] = 1 - This enables proper biasing of PLL analog circuitry */
MAINPLLCTL1 |= (1 << MAIN_ENSAT_OFFSET);
if(debug_info_on){
GEL_TextOut("(2a) MAINPLLCTL1 = %x\n",,,,, MAINPLLCTL1);
}
/* Step 2b: Set PLLCTL[PLLEN] = 0 This enables bypass in PLL controller MUX */
PLL1_PLLCTL &= ~(1 << PLLEN_OFFSET);
if(debug_info_on){
GEL_TextOut("(2b) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
}
/* Step 2c: Set PLLCTL[PLLENSRC] = 0 - This enables PLLEN to control PLL controller MUX */
PLL1_PLLCTL &= ~(1 << PLLENSRC_OFFSET);
if(debug_info_on){
GEL_TextOut("(2c) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
}
/* Step 2d: Wait 4 reference clock cycles (slowest of ALTCORE or SYSCLK) to make sure
that the PLL controller MUX switches properly to bypass. */
if(debug_info_on){
GEL_TextOut("(2d) Delay...\n",,,,,);
}
for(i = 0; i < delay; i++); // this delay is much more than required
/* Step 2e: Set SECCTL[BYPASS] = 1 - enables bypass in PLL MUX */
PLL1_SECCTL |= (1 << BYPASS_OFFSET);
if(debug_info_on){
GEL_TextOut("(2e) SECCTL = %x\n",,,,, PLL1_SECCTL);
}
/* Step 2f: Set PLLCTL[PLLPWRDN] = 1 - power down the PLL */
PLL1_PLLCTL |= (1 << PLLPWRDN_OFFSET);
if(debug_info_on){
GEL_TextOut("(2f) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
}
/* Step 2g: Wait for at least 5us for the PLL to power down */
if(debug_info_on){
GEL_TextOut("(2g) Delay...\n",,,,,);
}
for(i = 0; i < delay; i++); // this delay is much more than required
/* Step 2h: Set PLLCTL[PLLPWRDN] = 0 - Power the PLL back up */
PLL1_PLLCTL &= ~(1 << PLLPWRDN_OFFSET);
if(debug_info_on){
GEL_TextOut("(2h) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
}
}
else{ // PLL bypass disabled - Execute PLL setup for PLL that has previously been locked (skip to Step 3)
if(debug_info_on){
GEL_TextOut("Detected PLL bypass disabled: SECCTL[BYPASS] = %x\n",,,,, BYPASS_val);
}
/* Step 3a: Set PLLCTL[PLLEN] = 0 This enables bypass in PLL controller MUX */
PLL1_PLLCTL &= ~(1 << PLLEN_OFFSET);
if(debug_info_on){
GEL_TextOut("(3a) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
}
/* Step 3b: Set PLLCTL[PLLENSRC] = 0 - This enables PLLEN to control PLL controller MUX */
PLL1_PLLCTL &= ~(1 << PLLENSRC_OFFSET);
if(debug_info_on){
GEL_TextOut("(3b) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
}
/* Step 3c: Wait 4 reference clock cycles (slowest of ALTCORE or SYSCLK) to make sure
that the PLL controller MUX switches properly to bypass. */
if(debug_info_on){
GEL_TextOut("(3c) Delay...\n",,,,,);
}
for(i = 0; i < delay; i++); // this delay is much more than required
}
/* Step 4: Programming PLLM[5:0] in the PLLM register of the PLL controller and
programming PLLM[12:6] in the MAINPLLCTL0 register */
PLL1_PLLM &= PLLM_MASK; // clear the PLLM[5:0] bit field
PLL1_PLLM |= ~PLLM_MASK & (PLLM_val - 1); // set the PLLM[5:0] bit field to the 6 LSB of PLLM_val
if(debug_info_on){
GEL_TextOut("(4)PLLM[PLLM] = %x\n",,,,, PLL1_PLLM);
}
MAINPLLCTL0 &= MAIN_PLLM_MASK; // clear the PLLM[12:6] bit field
MAINPLLCTL0 |= ~MAIN_PLLM_MASK & (( (PLLM_val - 1) >> 6) << MAIN_PLLM_OFFSET); // set the PLLM[12:6] bit field to the 7 MSB of PLL_val
if(debug_info_on){
GEL_TextOut("MAINPLLCTL0 = %x\n",,,,, MAINPLLCTL0);
}
/* Step 5: Programming BWADJ[7:0] in the MAINPLLCTL0 register and BWADJ[11:8] in MAINPLLCTL1 register */
MAINPLLCTL0 &= MAIN_BWADJ0_MASK; // clear the MAIN_BWADJ0 bit field
MAINPLLCTL0 |= ~MAIN_BWADJ0_MASK & ((BWADJ_val - 1) << MAIN_BWADJ0_OFFSET); // set the MAIN_BWADJ[7:0] bit field to the 8 LSB of BWADJ_val
if(debug_info_on){
GEL_TextOut("(5) MAINPLLCTL0 = %x\n",,,,, MAINPLLCTL0);
}
MAINPLLCTL1 &= MAIN_BWADJ1_MASK; // clear the MAIN_BWADJ1 bit field
MAINPLLCTL1 |= ~MAIN_BWADJ1_MASK & (( (BWADJ_val - 1) >> 8) << MAIN_BWADJ1_OFFSET); // set the MAIN_BWADJ[11:8] bit field to the 4 MSB of BWADJ_val
if(debug_info_on){
GEL_TextOut("(5) MAINPLLCTL1 = %x\n",,,,, MAINPLLCTL1);
}
/* Step 6: Programming PLLD[5:0] in the MAINPLLCTL0 register */
MAINPLLCTL0 &= MAIN_PLLD_MASK; // clear the PLLD bit field
MAINPLLCTL0 |= ~MAIN_PLLD_MASK & (PLLD_val - 1); // set the PLLD[5:0] bit field of PLLD to PLLD_val
if(debug_info_on){
GEL_TextOut("(6) MAINPLLCTL0 = %x\n",,,,, MAINPLLCTL0);
}
/* Step 7: Programming OD[3:0] in the SECCTL register */
PLL1_SECCTL &= OUTPUT_DIVIDE_MASK; // clear the OD bit field
PLL1_SECCTL |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET; // set the OD[3:0] bit field of PLLD to OD_val
if(debug_info_on){
GEL_TextOut("(7) SECCTL = %x\n",,,,, PLL1_SECCTL);
}
/* Step 8: Following steps are needed to change the default output dividers */
/* Step 8a: Check that the GOSTAT bit in PLLSTAT is cleared to show that no GO
operation is currently in progress*/
if(debug_info_on){
GEL_TextOut("(8a) Delay...\n",,,,,);
}
while((PLL1_STAT) & 0x00000001);
/* Step 8b: Program the RATIO field in PLLDIVn to the desired new divide-down rate.
If RATIO field is changed, the PLL controller will flag the change in the
corresponding bit of DCHANGE*/
PLL1_DIV3 = (PLLDIV3_val-1) | 0x8000; //Set PLLDIV3
PLL1_DIV4 = (PLLDIV4_val-1) | 0x8000; //Set PLLDIV4
PLL1_DIV7 = (PLLDIV7_val-1) | 0x8000; //Set PLLDIV7
if(debug_info_on){
GEL_TextOut("PLL1_DIV3 = %x\n",,,,, PLL1_DIV3);
GEL_TextOut("PLL1_DIV4 = %x\n",,,,, PLL1_DIV4);
GEL_TextOut("PLL1_DIV7 = %x\n",,,,, PLL1_DIV7);
}
/* Step 8c: Set GOSET bit in PLLCMD to initiate the GO operation to change the divide
values and align the SYSCLKs as programmed */
PLL1_CMD |= 0x00000001;
/*Step 8d/e: Read the GOSTAT bit in PLLSTAT to make sure the bit returns to 0 to
indicate that the GO operation has completed */
if(debug_info_on){
GEL_TextOut("(8d/e) Delay...\n",,,,,);
}
while((PLL1_STAT) & 0x00000001);
/* Step 9: Set PLLCTL[PLLRST] = 1 - Assert PLL reset (Previously Step 3)*/
PLL1_PLLCTL |= (1 << PLLRST_OFFSET);
/* Step 10: Wait for the at least 7us for the PLL reset properly (128 CLKIN1 cycles) */
if(debug_info_on){
GEL_TextOut("(10) Delay...\n",,,,,);
}
for(i=0;i<delay;i++);
/* Step 11: Set PLLCTL[PLLRST] = 0 - De-Assert PLL reset */
PLL1_PLLCTL &= ~(1 << PLLRST_OFFSET);
/* Step 12: Wait for PLL to lock (2000 CLKIN1 cycles) */
if(debug_info_on){
GEL_TextOut("(12) Delay...\n",,,,,);
}
for(i=0;i<delay;i++);
/* Step 13: In SECCTL, write BYPASS = 0 (enable PLL mux to switch to PLL mode) */
PLL1_SECCTL &= ~(1 << BYPASS_OFFSET);
if(debug_info_on){
GEL_TextOut("(13) SECCTL = %x\n",,,,, PLL1_SECCTL);
}
if(debug_info_on){
GEL_TextOut("(Delay...\n",,,,,);
}
for(i=0;i<delay;i++);
if(debug_info_on){
GEL_TextOut("(Delay...\n",,,,,);
}
for(i=0;i<delay;i++);
/* Step 14: In PLLCTL, write PLLEN = 1 to enable PLL mode */
PLL1_PLLCTL |= (1 << PLLEN_OFFSET);
if(debug_info_on){
GEL_TextOut("(14) PLLCTL = %x\n",,,,, PLL1_PLLCTL);
}
/* Step 15: Lock Boot Config Registers */
KICK0 = 0x00000000;
KICK1 = 0x00000000;
GEL_TextOut("PLL has been configured (CLKIN * PLLM / PLLD / PLLOD = PLLOUT):\n",,,,,);
GEL_TextOut("PLL has been configured (%f MHz * %d / %d / 2 = %f MHz)\n",,,,, CLKIN_val, PLLM_val, PLLD_val, (CLKIN_val * PLLM_val / PLLD_val / 2) );
}
Set_Tetris_Pll(int index)
{
unsigned int BWADJ_val;
unsigned int OD_val;
unsigned int PLLM_val;
float CLKIN_val;
int i;
GEL_TextOut("Switching on ARM Core 0\n",,,,,);
TETRIS_CPU0_PDCTL = 0x00000000;
TETRIS_CPU0_PTCMD = 0x00000001;
GEL_TextOut("Switching on ARM Core 1\n",,,,,);
TETRIS_CPU1_PDCTL = 0x00000000;
TETRIS_CPU1_PTCMD = 0x00000001;
GEL_TextOut("Switching on ARM Core 2\n",,,,,);
TETRIS_CPU2_PDCTL = 0x00000000;
TETRIS_CPU2_PTCMD = 0x00000001;
GEL_TextOut("Switching on ARM Core 3\n",,,,,);
TETRIS_CPU3_PDCTL = 0x00000000;
TETRIS_CPU3_PTCMD = 0x00000001;
if(index == 1){ // 125 MHz -> 1.0 GHz
CLKIN_val = 125; // setup CLKIN to 125 MHz
PLLM_val = 16; // setup PLLM (PLL multiplier) to x20
OD_val = 2; // setup OD to a fixed /2
}
else if(index == 2){ // 125 MHz -> 1.4 GHz
CLKIN_val = 125; // setup CLKIN to 125 MHz
PLLM_val = 22; // setup PLLM (PLL multiplier) to x28
OD_val = 2; // setup OD to a fixed /2
}
else if(index == 3){ // 174.825MHz -> 1.4 GHz
CLKIN_val = 174.825; // setup CLKIN to 174.825 MHz
PLLM_val = 16; // setup PLLM (PLL multiplier) to x16
OD_val = 2; // setup OD to a fixed /2
}
BWADJ_val = (PLLM_val-1) >> 1; // setup BWADJ to be 1/2 the value of PLLM
OD_val = 2; // setup OD to a fixed /2
/* Step 1: Unlock Boot Config Registers */
KICK0 = KICK0_UNLOCK;
KICK1 = KICK1_UNLOCK;
/* Step 1: Unlock Boot Config Registers */
CHIP_MISC1 &= ~(1 << ARMPLL_ENABLE_OFFSET);
//Step 2 and 6 : Assert SEC PLL Reset
ARMPLLCTL1 = ((1 << ARM_PLLCTL1_RESET_OFFSET) | (1 << ARM_PLLCTL1_ENSTAT_OFFSET));
//Step 3 : set PLL in bypass
ARMPLLCTL0 |= (1 << ARM_PLLCTL0_BYPASS_OFFSET);
//Step 4 and 5 : Change CLKF/OD/BWADJ etc. for SEC PLL
ARMPLLCTL0 = ((BWADJ_val << ARM_PLLCTL0_BWADJ_OFFSET) |
((OD_val-1) << ARM_PLLCTL0_OD_OFFSET)|
((PLLM_val-1) << ARM_PLLCTL0_PLLM_OFFSET));
//Step 7 : Make sure the resets are held for 5us
for(i = 0; i < 200000; i++);
//Step 8 : Remove SEC PLL reset
ARMPLLCTL1 = (1 << ARM_PLLCTL1_ENSTAT_OFFSET); //This drives ARM_PLL1_RESET_OFFSET = 0
//Step 9 : Wait for PLL to lock (4000 CLKIN1 cycles)
for(i = 0; i < 4000; i++);
//Step 10 : Get the PLL out of Bypass
ARMPLLCTL0 &= ~(1 << ARM_PLLCTL0_BYPASS_OFFSET);
//Step 11 : Set Output of ARM PLL as input to ARM
CHIP_MISC1 |= (1 << ARMPLL_ENABLE_OFFSET);
//Step 11: Lock Boot Config Registers
KICK0 = 0x00000000;
KICK1 = 0x00000000;
GEL_TextOut("ARM PLL has been configured (%f MHz * %d / %d = %f MHz)\n",,,,, CLKIN_val, PLLM_val, OD_val, (CLKIN_val * PLLM_val)/OD_val);
}
此致
尚卡里